Lpc2000

When I enter debug mode through jtag I made following:
01. read R0 (arm or thuumb instruction)
02. read PC (arm or thumb instruction)
03. If THUMB detected switch to arm (bx)
04. read r1 to r14 (arm instructions)
05. read cpsr and spsr (arm instructions)
06. modify read cpsr to get proper information about mode (arm/thumb 
bit) - only in host software.

When I exit from debug state:
10. restore r1 to r15 (arm instruction - r15 is modified to reflect 
correct address after 12)
11. restore cpsr
12. restore r0 (arm or thumb instruction)

I have a problem in step 11-13 when I have to restore cpsr. I don't 
make a jump at the end of restore.
Do I have to restore cpsr with thumb mode depended on the state I 
entered the debug state? 
I don't know if the next instruction after cpsr resore should be also 
depended on the state I entered debug mode.
Sometimes when I exit in thumb (I have entered in thumb) I got 
exception (undefined instruction), but not always. 
What will happen if the processor receive interrupt durring debug mode -
 should I exit in the state I entered debug mode or should I check 
interrupt flag before exit?
Maybe I'm making something wrong - could someone describe how to do it 
properly?

Does anyone know the proper way of exit from debug state to the thumb
running state? This is not described in any available arm documents.

--- In lpc2000@yahoogroups.com, "radoslaw_mitura"
<radoslaw_mitura@y...> wrote:

>
> When I enter debug mode through jtag I made following:
> 01. read R0 (arm or thuumb instruction)
> 02. read PC (arm or thumb instruction)
> 03. If THUMB detected switch to arm (bx)
> 04. read r1 to r14 (arm instructions)
> 05. read cpsr and spsr (arm instructions)
> 06. modify read cpsr to get proper information about mode (arm/thumb 
> bit) - only in host software.
> 
> When I exit from debug state:
> 10. restore r1 to r15 (arm instruction - r15 is modified to reflect 
> correct address after 12)
> 11. restore cpsr
> 12. restore r0 (arm or thumb instruction)
> 
> I have a problem in step 11-13 when I have to restore cpsr. I don't 
> make a jump at the end of restore.
> Do I have to restore cpsr with thumb mode depended on the state I 
> entered the debug state? 
> I don't know if the next instruction after cpsr resore should be also 
> depended on the state I entered debug mode.
> Sometimes when I exit in thumb (I have entered in thumb) I got 
> exception (undefined instruction), but not always. 
> What will happen if the processor receive interrupt durring debug mode -
>  should I exit in the state I entered debug mode or should I check 
> interrupt flag before exit?
> Maybe I'm making something wrong - could someone describe how to do it 
> properly?
>

>     Does anyone know the proper way of exit from debug state to the thumb
>  running state? This is not described in any available arm documents.

The way you describe it in your previous mail sounds good:

>  > When I exit from debug state:
>  > 10. restore r1 to r15 (arm instruction - r15 is modified to reflect
>  > correct address after 12)
>  > 11. restore cpsr
>  > 12. restore r0 (arm or thumb instruction)

The only question is what will happen with the content of r15 during steps
11 and 12 (the LSB must stay 1 in order to jump to thumb mode).

I have not even reached thumb mode yet, I have some problems reading
registers after execution of a system speed LDR r1,[r0]. It seems the
RESTART has some side effects such that I am not able to do normal CPU
register reads anymore (reading the ICE registers looks Ok so scanchain
works).

I have planned to do some monitoring on the JTAG signals of a working JTAG
pod. I will also look at thumb at that time and keep you informed.

Regards,

    Rob

I'll be waiting to hear the news from you.
Thanks a lot.

Radek

--- Rob Jansen <rob@...> wrote:

> >     Does anyone know the proper way of exit from
> debug state to the thumb
> >  running state? This is not described in any
> available arm documents.
> 
> The way you describe it in your previous mail sounds
> good:
> 
> >  > When I exit from debug state:
> >  > 10. restore r1 to r15 (arm instruction - r15 is
> modified to reflect
> >  > correct address after 12)
> >  > 11. restore cpsr
> >  > 12. restore r0 (arm or thumb instruction)
> 
> The only question is what will happen with the
> content of r15 during steps
> 11 and 12 (the LSB must stay 1 in order to jump to
> thumb mode).
> 
> I have not even reached thumb mode yet, I have some
> problems reading
> registers after execution of a system speed LDR
> r1,[r0]. It seems the
> RESTART has some side effects such that I am not
> able to do normal CPU
> register reads anymore (reading the ICE registers
> looks Ok so scanchain
> works).
> 
> I have planned to do some monitoring on the JTAG
> signals of a working JTAG
> pod. I will also look at thumb at that time and keep
> you informed.
> 
> Regards,
> 
>     Rob
> 
> 



		
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First I want to say what I great groups this is.  I have been 
learning a lot from reading current posts and posts in the archive.

I was searching for an answer to a problem that I am currently 
encountering and I found this thread from last year.  I have been 
working on my own debugger and got most of the core functionality to 
work when the debug state has been entered in ARM mode.  When I enter 
the debug state from THUMB mode, I can switch back into ARM mode, 
read/write registers and read/write memory.  However, I can't exit 
the debug state in THUMB mode.

I use a BX R0 instruction to reenter THUMB mode and then use a "B 
sigened_11bit_immediate_offset" THUMB instruction (bit 33 of the 
previous NOP instruction is set to indicate that the system should re-
enter full-speed mode).  If I then enter the RESTART JTAG command and 
enter the run/idle state of JTAG, the DSR will show that the core is 
in Thumb mode but it ends up back in the debug state.  

Re-entering ARM mode and dumping the registers at this point results 
in garbage.  Many of the registers come back as 0 (including R15) but 
some do have other non-zero values.  Even the CPSR is garbage (the 
mode bits are not valid.)

To make sure that I don't have some invalid THUMB instructions in my 
command sequence, I clear bit 33 of the penultimate NOP and don't 
bother to enter the RESTART JTAG command.  If I then re-enter ARM 
mode here and dump the registers, they all look correct.  Even r15 
has the expected value.  This makes it appear to me that the 
instructions are restoring the context correct and performing the 
right branch but the core doesn't seem to like the THUMB Branch 
instruction being used to get it to re-enter full-speed mode.  A 
similar sequence is working for me in ARM mode (but I don't need to 
perform the BX instruction and I use a ARM variant of the Branch 
instruction instead).  Should I be using a different THUMB 
instruction as the last instruction before sending the RESTART 
command?

Thanks!
--- In lpc2000@yahoogroups.com, Radoslaw Mitura 
<radoslaw_mitura@y...> wrote:

> > >     Does anyone know the proper way of exit from
> > debug state to the thumb
> > >  running state? This is not described in any
> > available arm documents.