Lpc2000

Hello,

I am using Olimex "LPC-P2106" board with JTAG pins P0.17-P0.21
(primary group).
I prototype with LCD, so I need almost all pins set as "out" or "io".
I there any trick to set pins P0.22-P0.30 (used for alternative JTAG
and Trace) to output mode, while using the JTAG debugging?
It looks like using them as "input" is not an issue (P0.31 is used for
button on "LPC-P2106") but they do not switch to "output" in Debug
mode. The JTAG shows the values of "direction" and "out" registers
changing properly, but actual levels on pins look to remain "input"...

I have written the application and it is working fine in "release"
mode (executed from flash), but I'd like to have debug possibility and
also run it from RAM...

The UG (page 79) says "Function control for the pins P0.17-P0.31 is
effective only when the DBGSEL input is pulled low during Reset".
Actually it looks like the pins are set as GPIO at reset, but the
IODIR setting to output has no effect with DBGSEL=1 during Reset...


Thanks for help!

Em Ter 09 Mai 2006 06:18, volodymyr_tymchyshyn escreveu:
> Hello,
>
> I am using Olimex "LPC-P2106" board with JTAG pins P0.17-P0.21
> (primary group).
> I prototype with LCD, so I need almost all pins set as "out" or "io".
> I there any trick to set pins P0.22-P0.30 (used for alternative JTAG
> and Trace) to output mode, while using the JTAG debugging?
> It looks like using them as "input" is not an issue (P0.31 is used for
> button on "LPC-P2106") but they do not switch to "output" in Debug
> mode. The JTAG shows the values of "direction" and "out" registers
> changing properly, but actual levels on pins look to remain "input"...
>
> I have written the application and it is working fine in "release"
> mode (executed from flash), but I'd like to have debug possibility and
> also run it from RAM...
>
> The UG (page 79) says "Function control for the pins P0.17-P0.31 is
> effective only when the DBGSEL input is pulled low during Reset".
> Actually it looks like the pins are set as GPIO at reset, but the
> IODIR setting to output has no effect with DBGSEL=1 during Reset...
>
>
> Thanks for help!
>
What I know for sure, is that you lose 15 pins with Jtag enabled at reset, ie, 
by pulling down DBGSEL at reset. With DBGSEL set so, there are no ways to use 
the remaining IOs that are not used by Jtag. Period. 
But, you have an alternative. You can enable Jtag by software (or better, by 
firmware). I dont remeber how, by I found in a site a text explaining how to 
do it (I didnt care about because I dont wish to do it), but its possible. I 
think (and I can be wrong here) that doing so you need to upload your 
firmware by ISP, and I dont know if you can upload a program to the RAM to 
execute it, by enabling Jtag by software (of course I know that it is 
possible enabling by hardware).
All in all, my develpment process is so: I try to debug my firmware routine by 
routine, via Jtag. When its time to put all together, and if I need all IOs, 
the risc of bugs are lesser. But I agree that thats not the best way...

volodymyr_tymchyshyn wrote:

>Hello,
>
>I am using Olimex "LPC-P2106" board with JTAG pins P0.17-P0.21
>(primary group).
>I prototype with LCD, so I need almost all pins set as "out" or "io".
>I there any trick to set pins P0.22-P0.30 (used for alternative JTAG
>and Trace) to output mode, while using the JTAG debugging?
>It looks like using them as "input" is not an issue (P0.31 is used for
>button on "LPC-P2106") but they do not switch to "output" in Debug
>mode. The JTAG shows the values of "direction" and "out" registers
>changing properly, but actual levels on pins look to remain "input"...
>
>  
>
I'm using the Secondary JTAG for debugging in my board and disabling the 
Primary JTAG for use as I/O.

Pins P0.27..P0.31 goto my JTAG unit, all other JTAG group signals are 
used for I/O.  There is no "interference" that I've seen.  You have to 
do two things to use the secondary JTAG: enable it and provide a startup 
delay.

To use the Secondary JTAG, I place the following into my crt0.S file:

================ begin crt0.S ==================
__undf: b     .                         // undefined
__swi:  b     .                         // SWI
__pabt: b     .                         // program abort
__dabt: b     .                         // data abort
__irq:  b     .                         // IRQ
__fiq:  b     .                         // FIQ
#endif

JTAG2:
   .word 0x55400000
PINSELREG:
   .word 0xe002c004

        .size _boot, . - _boot
        .endfunc


// Setup the operating mode & stack.
// ---------------------------------
        .global _start, start, _mainCRTStartup
        .func   _start
_start:
start:
_mainCRTStartup:

// Initialize Interrupt System
// - Set stack location for each mode
// - Leave in System Mode with Interrupts Disabled
// -----------------------------------------------
;
      ldr   r0, JTAG2
      ldr   r1, PINSELREG
      str   r0, [r1]       // activate secondary JTAG port.
;
      mov   r3, #0x10000
startdelay:
      subs  r3, r3, #1
      bne   startdelay     // give debugger time to catch us.
;
        ldr   r0,=_stack
        msr   CPSR_c,#MODE_UND|I_BIT|F_BIT // Undefined Instruction Mode
        mov   sp,r0
================ snip =======================


The above will turn off the Primary JTAG, turn on the Secondary JTAG and 
allow a delay for the JTAG pod to "catch" the processor. 

No, I do not believe that you can also use the Secondary JTAG pins as 
I/O AND use them for the JTAG functions at the same time...

TomW




-- 
Tom Walsh - WN3L - Embedded Systems Consultant
http://openhardware.net, http://cyberiansoftware.com
"Windows? No thanks, I have work to do..."
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