Minimalist dynamic params on DS.
2004-06-16 by nonuckingfumber
Maybe I am missing something, but the datasheet for the 210x (5th Feb 2004) seems to have minimalistic parametrs. The max input frequency at fosc input is specified for ext source, crystal and with the PLL. The highest value is ext. source @ 50MHz Section on the PLL notes that the max PLL multiplier will be 6 on this chip. The bulleted features at the start of the data sheet states that Max clok speed is 60MHz. The DS notes that one of the reasons for having a divider for access to the VFB is that this is not capable of running at full CPU speed. Put it all together then I assume (if using a parameter from the 'features' list is OK) that the max CPU frequency is 60MHz but of course I must use the PLL to get this (probably 4 x from a 14,7MHz quartz). It does not say how long I should allow for the PLL to stabalize. Nor does it say how fast the VFB can run at. It says it resets to /4 to ensure the VFB runs at boot. Given that the max input is 50MHz and no PLL is present at reset, one can only assume that it cannot support 25MHz, or it would be possible to reset the bus to /2. Checked out the app notes on the Phillips site and there is no additional info there either. I hate to be pedantic but I am trying to minimise baud rate error on obsure high speed rates, and this very much depends on the VFB clock.