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SSP on IAR LPC2148 KS

SSP on IAR LPC2148 KS

2005-10-15 by joelw@indyelectronics.com

I have a IAR LPC2148 board and am having trouble getting any output on the
SSP port.  I can wiggle the SPI0 port just fine.  No dice on the SSP port.
 Once data is written into the data register SSPSR changes as expected,
but nothing transmits.  The intent is 8-bit master SPI.  Oddly in user
manual the CPOL bit for SPI0 and SPI1 means two different things.  And
I've tried this with a SPI slave connected as well as nothing connected. 
SSEL1 has a pull-up, although I don't believe this is relavant with the
SSP port on the LPC2148.  PCONP has SSP enabled.  What am I missing?


#define P0_17 0x02
#define P0_18 0x04
#define P0_19 0x06
#define P0_20 0x08
#define DSS   0x07  /* Data Size 8-bit */
#define CPHA     7  /* Clock Out Phase */

PINSEL1 |= ((2<<P0_17)|(2<<P0_18)|(2<<P0_19)|(2<<P0_20));
SSPCR0   = (1<<CPHA) | DSS;
SSPCPSR  = 120;  /* random even value between 2 and 254 */

SSPDR = 0x55; /* TFE, TNF, and BSY bits change state in SSPSR */


Regards,
Joel

Re: [lpc2000] SSP on IAR LPC2148 KS

2005-10-15 by joelw@indyelectronics.com

I just love it when you find the answer the moment after you click send!
Show quoted textHide quoted text
> I have a IAR LPC2148 board and am having trouble getting any output on the
> SSP port.  I can wiggle the SPI0 port just fine.  No dice on the SSP port.
>  Once data is written into the data register SSPSR changes as expected,
> but nothing transmits.  The intent is 8-bit master SPI.  Oddly in user
> manual the CPOL bit for SPI0 and SPI1 means two different things.  And
> I've tried this with a SPI slave connected as well as nothing connected.
> SSEL1 has a pull-up, although I don't believe this is relavant with the
> SSP port on the LPC2148.  PCONP has SSP enabled.  What am I missing?
>
>
> #define P0_17 0x02
> #define P0_18 0x04
> #define P0_19 0x06
> #define P0_20 0x08
> #define DSS   0x07  /* Data Size 8-bit */
> #define CPHA     7  /* Clock Out Phase */
>
> PINSEL1 |= ((2<<P0_17)|(2<<P0_18)|(2<<P0_19)|(2<<P0_20));
> SSPCR0   = (1<<CPHA) | DSS;
> SSPCPSR  = 120;  /* random even value between 2 and 254 */
>
> SSPDR = 0x55; /* TFE, TNF, and BSY bits change state in SSPSR */
>
>
> Regards,
> Joel
>
>
>
>
>
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