Message 20538     From: "xylotex" 
Date: Thu Aug 11, 2005  12:40 pm
Subject: Re: SLA7062 schematic


Additional comments

Hi,

The reset that goes through the OR gates puts the driver chips in to a known "reset" state. Power up will cause this to happen, or if you bring one of the lines on the header J8 high, this will happen. The original idea was based on a description in the Allegro datasheet that reset would also disable the drives. 

It does NOT disable the drives, only resets the internal circuitry. There was a problem translating the text from Japanese to English that caused this "reset" description problem.


The connect J1 (con5) simply has all unused parallel port I/O on it. 

The connector J8 (con6) is really obsolete (see above), and is unnecessary. If you take a look at the actual documentation for the drive on the Xylotex yahoo site, you can see that I describe using 1N914 type diodes attached to the Vref point for disabling the drives through a regular switch to Vcc.

Yes AVBB is voltage up to about 44VDC. Typically, just use a rectified and filtered 24VAC transformer for power. This is cheap and easy, and will give about 36VDC.

There are two sides to the GND, the power and the logic side. The power side is the bigger arrow pointing down. The logic side is the smaller arrow with GND under it. These are separated by a ferrite bead. If you don't want to have the bead in the design, simply connect both sides together. You probably will not see a significant difference anyway.

[Dave's notes ; the data sheet says to use a Star ground, so this bridge between the two grounds may not require the ferrite bead, but it does offer a known place on the board where the two power supply grounds meet.]

I opted to use the simple switcher because a normal linear regulator trying to provide +5VDC from 44VDC would get very hot.

Jeff