[sdiy] VC ADSR

[Paul Maddox]

Dear all,

 Im thinking of haveing a go at a VCADSR module...

 Couple of questions..

I know that the attack phase of most Capacitor based ADSR is not liked by
many..
should I try and get a linear attack stage, then log Decay/release?

  Should I include an option for Lin/Log?
ie,

Lin ;- Linear Attack, Decay AND release
Log;- Linear attack, log decay and log release

  Also what about trigger/retrigger/gate?

 Should I have an option to allow retriggering (ie reset whole EG the moment
the garte rises)
or should I use seperate trig/gate lines?

  Paul Maddox
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