[sdiy] SRAM like 5101

[Rainer Buchty]

> However I'm not sure if they have separate I/O.

The haven't.

> Since I'm at the office, I don't have an ancient data book at hand right
> now.

www.chipdir.org and www.partminer.com are your friends :)

(Of course I still keep my "geriatronic bibles" - web pages come and
go...)

> In that case it's probably better to do a redesign, in order to use
> something like 6116s (2kx8). Of course it will depend on the surrounding
> circuit if this is easily feasible. IMHO, adding a couple of 'LS245
> 3state buffers would be better than relying on obsolete parts, but gate
> timing may require some thinking.

I don't think that timing would really be an issue since the 5101 has
650ns access time according to Chipdir (can you say "slow"?); now just
take one of those 32k cache RAMs (you instantly get tons of them for free
when cannibalizing old PC boards) or - in case these beasts are 3.3V
operation ony which I haven't checked yet - grab a 6116, add two 74HC244
(or '245 for nicer layout), maybe a '139 for creating all the variants
over CS and WR we need, and you should be set.

For real overkill, you could of course replace all RAMs by a small Xilinx
FPGA and just use its block RAM :)

But... Does the PS3200 really access in and out data buses separately or
are these buses merged to a common data bus anyway which then is accessed
by a CPU or some simple control logic? In that case it might be easier to
tap the common data bus.

Rainer

-- 

Rainer Buchty, LRR, Technical University of Munich
Phone: +49 89 289-28401, Fax +49 89 289-28232, Room S3240