[sdiy] Speaking of CMOS....

[Peter Grenader]

I'm working with a 4053 that specs a 15 p-p volt max for analog information
going through it.  It seems a pair of 8 voltge regulators did the trick. One
of the signals going into it however will be from CMOS and is a 11 high
static state logic enable signal.

Would it be wise for me to  pop a PNP in there instead to keep the 11 volts
the hell away form the 4052, given thats 3 volts higher than it's Vdd?

I'm thinbking yes, but wanted some guidedance from the masters here.
\thanks in advance,

Peter