[sdiy] Re: Daffy CMOS ASCIImatic

[Scott Gravenhorst]

That's excellent.  It's really quite simple.  I see how 
the integrator works better, the source of each transistor 
goes to a virtual ground summing node.

How is this powered, single supply? (LM324?)


Thanks.

=?iso-8859-1?Q?Ren=E9?= Schmitz <uzs159 at uni-bonn.de> wrote:
>At 09:52 29.04.02, Scott Gravenhorst wrote:
>>Ok, then it looks like a lot depends on the nature of the load.
>>I'm starting to think that my end purpose idea is a waste of
>>time.  That being: use an opamp to scale and buffer an input=20
>>signal.  The output of the opamp goes to one end of the parallel
>>complementary MOSFETs.  The other side of the transistor pair=20
>>goes to a capacitor to ground.  The output of the circuit is=20
>>point where the cap meets the transistors.  Would this function
>>as a VC LPF?  Am I foolishly thinking this could work like one=20
>>of the stages of an OTA based VC-SVF?
>
>I'd use invertors as integrators. The problem with a cap to GND is=20
>that as the voltage over the cap changes, it changes the gate to=20
>source voltage.
>
>I've uploaded a small circuit I did some time ago, where I used the=20
>MOSFETs (albeit just the n-channel) of a 4007 for a filter. I think=20
>one can even replace the opamps by invertors, by shifting the GND potential=
>=20
>to Ub/2 (or by using symmetric power for the CMOS).
>
>http://www.uni-bonn.de/~uzs159/temp/vcf4007_s.gif
>
>It has linearisation for the "resistor", and I could use levels ~200mV.
>
>Cheers,
> Ren=E9
>
>
>--=20
>uzs159 at uni-bonn.de
>http://www.uni-bonn.de/~uzs159
>
>=20
>

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