[sdiy] Delays: how?

[Magnus Danielson]

From: MED <teenagewasteland at prodigy.net>
Subject: [sdiy] Delays: how?
Date: Wed, 25 Dec 2002 16:03:35 -0600

> 	Okay, the BBD source seems to have dried up (along with the whole 
> "sounding horrible") and this raises the question: what now?
> I want to make a delay with a decent time (something like 1 second). 
> Feedback should be adjustable from same level (feeding back until 
> hard-clipping catches it) to silent. Preferable would be control over 
> the feedback loop, like an effects chain (pitch shifting craziness, et 
> cetera)
> I have the feeling that a modern-component delay will be a 
> some-decent-bit-number ADC into a LOT of shift registers (same number of 
> lines as the resolution of the ADC/DAC, times however many are needed 
> for the delay time) into a DAC. Is there a better technique? Preferably 
> something simpler?

I think going for the ADC/DAC track and digital delay is indeed a
possible way. I think that a ADC chip and a DAC chip (say 16 bit or so),
a memory chip and then some CPLD or small FPGA would do the trick.
The question then comes if one should vary the sample-rate or if one
should change the offset between the read and write counters in the
memory. The technique that could be used is to run the memorychip as a
flexible buffer between two different clock domains (i.e. asynchronously)
which is a little more difficult to implement, but is really not that
much of a mystery these days (look in for instance the Xilinx appnotes).

Cheers,
Magnus