[sdiy] Delays: how?

[Ingo Debus]

Magnus Danielson wrote:
> The question then comes if one should vary the sample-rate or if one
> should change the offset between the read and write counters in the
> memory.

Varying the sample rate would require a fast ADC to get a decent delay 
time range (high sample rate for short delay).

I think varying the address offset (between read and write address) to 
modulate the delay time isn't that bad. There are single samples 
repeated or skipped when the delay time gets longer/shorter. If the 
modulation source is, say, a ramp, it becomes effectively a staircase. 
If this is still to "steppy", just increase the sample rate to make 
the stair steps finer. Memory chips are cheap.

There were digital delays that didn't use different read and write 
addresses to vary the delay time, but limited the address range 
instead (i.e. variable reset address for the address counter). This is 
of course next to useless for delay time modulation, since it only 
takes effect when the counter wraps around.

> The technique that could be used is to run the memorychip as a
> flexible buffer between two different clock domains (i.e. asynchronously)
> which is a little more difficult to implement, but is really not that
> much of a mystery these days (look in for instance the Xilinx appnotes).

Two different clocks? To get pitch shift effects? Or what would this 
be good for?

Ingo