[sdiy] BBDs and crap.

[René Schmitz]

Hi Batz, et al.

I tried this a couple of years ago. Never actually built the delay stuff, 
just checked the encoders. I found the encoders to be rather slow, so I'd 
lowered the time constants to speed up the operation and obtain higher 
fidelity. Thats where the constant slope delta encoding has its problems. 
So its "nonadaptive" delta modulation. ;-) So ultimately I went the route 
of copying the Adaptive DeltaLabs encoder as published in one of their 
patents. (The patent number is my homepage.) I think there ought to be 
encoder circuits possible in complexity between the delta lab and the 
simple encoder of your circuit. How one implements the delayline is then 
another matter. The AVR uC was the simplest method for me, and would work 
with both kinds of encoders. Your circuit surely had its impact on me, and 
is responsible for my homebrew delay experimentation. 

Cheers,
 René



At 04:35 03.09.02 +0930, you wrote:
>Y-ellow All.
>         Excuse me I'm very tired. Or is it the drugs? I can never tell.
>
>I'm pretty sure, that on my web page (God I don't even know what's on my 
>own web page.) is a circuit for a DDL which YOU ALL. are probably going to 
>find interesting at this point. I know I certainly did.
>
>It is possibly the simplest, kick-ass-est, way to achieve 
>long/short/sideways digital delays for about 10 bux in parts with quality 
>that'd knock 9 colours of snot out of a BBD.
>
>I never got the thing perfected onto a PCB because I needed to redesign 
>some kind of logic sequencer instead of the simple pulse delay (RC-CMOS 
>gate) arrangement. And my brain just wasn't in it at the time. The RC pulse 
>delay works as an echo type unit but for flanging etc, you really have to 
>lock it down with some hard logic.
>
>Basically it's a very simple sigma/delta modulator. Also known as 1bit 
>conversion. It uses a single 4164/41256 etc, memory chip as the storage 
>unit. OK I'm tired here so don't shot down this attempted description but 
>basically what you do is you differentiate at the front end and you 
>integrate at the other. You do this across a suitable capacitor at each end.
>
>When the thing powers up it finds it's own level. A CMOS gate output 
>constantly switches 1-0-1-0 at a given rate. When the gate output is "1" 
>the cap charges up. When it's "0" it discharges. The voltage across the cap 
>is compared with the incoming voltage with a comparator. If the cap voltage 
>is lower, the gate output is instructed to pump the cap up. If the cap is 
>higher,  it's discharged till it's equal. It does this at a reasonably high 
>speed. Though slower than you might think. The status of the comparator is 
>sampled at the clock rate and stored successively in memory locations in 
>the RAM chip. There is only one CAS/RAS count register as I recall. The 
>first cycle rips the data out and the second cycle replaces it with new 
>data. It just runs round the length of the RAM chip from one end to the 
>other. The faster the clock the shorter the delay. You can also cut down 
>the number of addresses used as well of course.
>
>At the ass end, it just does the opposite to the mouth end. The outgoing 1s 
>and zeros charge/discharge a cap and this doesn't even require any aliasing 
>because the cap is the aliasing filter as well.
>
>Clear as mud so far? Well go take a look. It's a lot simpler than it 
>sounds. And it does sound rather impressive considering. I messed with it 
>as a data communications system at one time too. Instead of the RAM chip I 
>just used a length of wire basically. You could use an RS485 driver or 
>something and a little bit of logic to encode the clock and you have a 
>robust digital audio transmission medium. Complete cheap-assed-bastard style.
>
>I never got back to this project because of the sequencer logic. My aim was 
>to find a way to program some of these little PALs I've got and put most of 
>the logic inside a single chip. But I still have no clue as to how to get 
>any joy from those things. I'm not sure if a 2051 would be fast enough. An 
>AVR probably would be but whether I get round to investigating AVRs is 
>another story entirely.
>
>This was not an original idea BTW. I saw the original circuit in, ooo 
>Wireless and Radio world???? It's on the web site anyway. I think I put the 
>original circuit up there (redrawn of course) not my bastardized attempts, 
>because there is still ample room for experimentation with this thing. But 
>I can tell you that I was pretty impressed with it and it certainly knocked 
>the blocks from under a BBD delay. More importantly, unlike the PT chips 
>(Which in all likelihood are just a sigma delta scheme similar to this one 
>anyway) there is ample scope for tayloring the circuit to the specific 
>needs of the device you're trying to build. For a Flanger/chorus unit, 
>you'd pump up the clock and  chop off some addresses to the RAM chip. If 
>memory serves I calculated in the sub 2mS delay time with good quality. Or 
>if longer delays are required you can stuff in bigger RAM chips. Prolly 
>getting huge delays if you wished.
>
>I can't think of anything more I can tell you off hand. You'll just have to 
>go look it up. But if anyone takes it on and comes up with something 
>interesting I'd love to hear about it.
>
>Hope this helps.
>
>Be absolutely Icebox.
>
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uzs159 at uni-bonn.de
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