68300

I have built prototype boards with TSC pulled low as indicated in the 
attached e-mail (with Motorola tech support).

The chips will NOT release reset (it stays low).
All of the pins that I have connected appear tristated, but in single 
chip mode this is to be expected...

I have the CPU configured as follows:
66.667MHz 45/55 duty cycle oscillator chip giving a clean 2X clock 
signal on a short lead.  I did not pin out CLKOUT so I have no access 
to this as a diagnostic.

MODCLK is hard wired low.
BERR is tied low (single chip mode) -- first I used 10K and now it is 
hard wire low...
HALT is tied high through 10K and is high
BKPT is tied high through 4.7K and is high

RST tied high through 1K but measures 60 mV... (will NOT release)

BGACK and BR are tied together and the pair is tied high through a 
10K resistor.  

NOTE that the BR & BGACK nodes are at 1.5V and do NOT appear to be 
tristated.  When I remove the 10K pull-up they remain at 1.5V. 

BR and BGACK should both be inputs... but the manual says they have B-
type output drivers.

Is it possible one of them is coming up as CSE or CS[0] and is 
pulling the other low?  





> 
> Dear Mr. Andle:
> 
> In reply to your Service Request SR 1-35542677 (see details below):
> 
> You are correct.  The 'F375 documentation has some errors in it.  
The TSC pin needs be pulled low for normal operation and pulled to 
Vdd for tristate operate.  Sorry for the incorrect information.  I 
have asked the factory to update this information in the data book.
> 
> ************ Details of your request: ************
> 
> Date Opened :   7/11/2002 11:48:59 AM
> Product :       MC68F375BGMZP33
> Topic :         Technical Request
> Subject:        68F375 erratta?  TSC
> 
> Description : 
> 
> page 4-69 says that asserting a logic low on TSC (I assume this 
means VSS) places the MCU into high impedance mode.
> 
> Please confirm that TSC-->VSS ENABLES outputs.