68300

I think I found the problem with my chips not coming out of reset...

It appears that, while the 68F375 *can* operate at 33.56 MHz from an
external clock, that it cannot do so with the X-bit clear.  That is, it
appears that the external signal needs to be 2X the system clock up to a
maximum external frequency of 33.56 MHz going into the X-stage divider.

In order to operate the 68F375 above 16.78 MHz, one must use a high symmetry
(which I have) clock AT the system frequency.  The 2X system clock,
low-symmetry option is NOT available much above 16.37 MHz (system) as this
appears to be the guaranteed (half) toggle frequency of the X-stage divider.

SO... when I used a 66.667 MHz external clock the X-stage divider is unable
to toggle at 66.667 MHz -- even IF the boot condition were X=0 to divide
this to a frequency the rest of the chip could use.

Ah, the perils of THINKING that you understand one Motorola chip just
because you understood the other...

(at least my solution is as simple as buying 33MHz oscillators or continuing
to debug with the 16.78MHz ones that I have)

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MC68F375 SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E) MOTOROLA
REFERENCE MANUAL Rev. 15 Oct 00 4-13

4.3.5 External Clock Mode
In external clock mode, the clock source, which should be 2x the desired
system frequency,
must be driven onto the EXTAL pin. This clock is used to generate the system
clock directly (the VCO is turned off). At reset, the system clock frequency
is one-half
the external clock frequency. If this frequency is the the maximum specified
system
clock frequency, it must not violate strict minimum duty cycle requirements.
A block
diagram of external clock mode is show in Figure 4-4.

In this mode, the six-stage Y divider and the one-stage X divider are placed
in the clock
output path such that the input clock may be divided down by as much as 128
to produce
the system clock. When this is done, it is not necessary to meet the input
duty
cycle restrictions. The Y bit divider is a six-stage divider chain whose
output tap is controlled
by the three Y register bits. The X bit divider is a single-stage divider
which is
bypassed when X is set to 1. X is 1 and Y is 0 after reset, so that the
system clock is
the same as the external clock.

NOTE
Setting Y to 7 has the same effect as setting it to 6; the maximum divisor
is 26. The X and Y bit dividers are in the output clock path.
Therefore, changing the X or Y bits in this mode causes the frequency
to change without a delay.
When the MC68F375 is configured in external clock mode, the VCO will be
turned off
to save power. Changing the unused W bits will have no effect.