68300

Scott,
 
I have seen the exact waveform you are describing.  Here is how a Power ON Reset sequence works.
 
1.  Reset is asserted low from the application of power.
2. Reset remains low until the SLOCK bit is set in the Clock Synthesizer Control Register.
3. Reset has a 2 system clock cycle period where it goes into a 3-state condition.
4. Reset is then asserted (as an output) to a logic 0 for 512 clock cycles.
5. At the end of the 512 clock cycles, the reset pin enters a 3-state condition for 10 system clock cycles.  If by the end of the 8th clock cycle, the reset pin has reached a logic 1, the reset pin becomes an input (at the end of the 10th cycle).
6.  The reset remains an input and program execution starts.
 
However, if the reset pin has not reached a logic 1 by the end of the 8th or 9th cycle, the internal control circuitry asserts the reset pin to a logic 0 for 512 cycles.
 
Then, go back to step 5 above.
 
I think that what you are seeing is that you have NO pull up resistor on RESET.  The "rise" that you are seeing is the reset pin floating during the 10 cycle period mentioned in step 5 above.
 
Put a 2 Kohm pull up on RESET and I think all your problems will go away.
 
Charlie

-----Original Message-----
From: Scott Newell [mailto:newell@...]
Sent: Wednesday, June 18, 2003 2:25 PM
To: 68300@yahoogroups.com
Subject: Re: [68300] Connecting to 332


>I started looking at the pins and found a waveform on the reset pin when the
>BDM is not connected. The signal is low and then starts to rise, it reaches
>up to 0 .4Vdd and then is pulled low again. Looks like a spiked waveform
>with the signal low for approximately 160ms.

What's the value of the pullup resistor on the reset pin?


newell



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