68300

Hi all,

I have a Benchmarq bq4842y battery backed ram RTC chip with INT* tied to 
IRQ7* directly (no pullup).

I have programmed PFPAR with a value of 0x80. DDRF is irrelevant but has a 
value of 0x13.

VBR is 0x100000. Location 0x10007C has 0x10E0C8 (address of the interrupt 
routine). Interrupt routine is declared as such and ends in RTE.

I have placed a breakpoint at the beginning of the interrupt routine (using 
SDS debugger) and the breakpoint never fires. When the RTC interrupt 
happens I can watch the INT* line go low and from that point on, when I try 
to halt the processor, SDS complains that it had to use a double bus fault 
to halt the processor. Prior to the interrupt the processor will halt properly.

If PFPAR is set to 0x00, I can always halt the processor properly even 
after the INT* line is asserted by the clock chip.

Any ideas?

Andrei

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Andrei Chichak               #200 10835-120 Street
Senior Software Developer    Edmonton, Alberta
Pulmonox Medical Inc.        Canada
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