68300

Keith.Wilson@...,

> I'm currently assuming that instructions like "ORI.X", "AND.X" use RMW bus 
> accessses.......  

Not quite. These use a separate read and a subsequent write cycle; in a 
single processor system, this is indivisible so you may assume for
your purpose they are RMW.
The only opcode using a true RMW cycle (AS does not get deasserted between
the read and write portions of the cycle) for the CPU32 is TAS  (test and set).
With write-only latches like yours, the thing to take care of is to
mask interrupts which might want to modify the latch while doing
"memory-copy read-write and latch write".
All this is valid in a signle processor system, I assume this is the case.

> My question - is there a list of RMW instructions for the CPU32 processor (68332)?? 

There used to be a book, "68k series programmers reference manual" or
something like that. I don't know whether it can be found nowadays,
asking Motorola should work. Perhaps it is on their website as a .pdf
file as well (I have never checked, I have my old paper copy).

Dimiter

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Dimiter Popoff
Transgalactic Instruments, Gourko Str. 25 b, 1000 Sofia, Bulgaria
http://transgalactic.freeyellow.com