68300

Greetings All

Are there general guidelines which can predict the
performance tradeoff of bus-width versus
memory-access-time? for example:

70nS , 16bit Flash memory
versus
120nS, 32bit Flash
when used on a 25MHz 68360.

Thanks in advance

Russell

On Thu, Aug 29, 2002 at 05:15:35PM +0200, rfowler wrote:
> Are there general guidelines which can predict the performance
> tradeoff of bus-width versus memory-access-time? for example:
>
> 70nS , 16bit Flash memory
> versus
> 120nS, 32bit Flash
> when used on a 25MHz 68360.

count the bus cycles.

unless you're running synchronously you'll have at least three bus
cycles plus wait states per bus access.  to transfer 32bits on the 16bit
part, you'll take two 3+wait cycles, giving you a total of 6+2*wait
cycles, where the 32bit part you'll only take 3+wait cycles.

it gets more complex if you're handling a lot of word or byte accesses,
which will be the same speed on the 32-bit part (3+wait) but would be
faster on the 16-bit part (3+smaller wait).

is there a reason you can't interleave two 16-bit parts?

-- 
  Aaron J. Grier  |   Frye Electronics, Tigard, OR   |  aaron@...