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Re: [AVR-Chat] Re: Voltage level translation

2009-04-08 by Roy E. Burrage

I'm sure you're correct, Graham.  I didn't look at it thoroughly as it 
just came through this morning on an EDN blast.

Novel?  Probably not, for those of us who have been doing this sort of 
thing for a while.  The intent was to address some of the issues brought 
forward by the occasional digital only folk who subscribe to this list.


REB



Graham Davies wrote:
> --- In AVR-Chat@yahoogroups.com, "Roy E. Burrage" <RBurrage@...> wrote:
>   
>> Since this comes up from time to time on the list:
>> http://focus.ti.com/lit/an/scea040/scea040.pdf
>>     
>
> I took a quick look at this, since I have a logic level translation problem in a product under development.  My impression is that some manager at TI has told some poor struggling application engineer that he's behind on his quota of application notes and he'd better get one out this afternoon.  Note, for example, that the circuit for using an open-drain FET as a level translator inverts the signal, which you almost never want.  Roy, is there anything in here that you think is novel?
>
> Graham.


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