On Thu, Aug 27, 2009 at 09:45:52AM -0600, Cat C wrote: > > Hi there, > > I am in a bit of a dilemma here, trying to choose the right chip for an application. > > One requirement is that I need to be able to generate some microsecond > (let's say between 1 - 100us) length pulses, the timing between them > about the same... kind of like this: > - a 40us pulse on one output > - a pause of 2 us > - a pulse of 2s on another output > > The good thing is that the uC doesn't need to do anything else in the > mean time. Yes, thats convenient but I'm thinking you should research the PWM capabilities of the AVR as all or almost all of what you want can be implemented in hardware. Specifically I'd look into doing it like this: Configure one Output Compare to generate the 40uS pulse. Run a wire from that OC to an Input Capture which on falling edge is set to start a PWM sequence of 2uS low followed by 2 seconds high. You have 2 seconds in software to figure out what to do next. When the 40uS pulse starts, arm the 2uS/2S system at the same time so that it starts while the 40uS output is high. Also do it here because you don't ever want the 2uS/2S thing to start until a 40uS thing has started. Am not certain the AVR hardware can do all of the above, but have seen similar in AVR and other places and would start looking hard at the datasheets to see if can preload the 2uS/2S sequence to start on external signal. As for the CPU clock, select a crystal for which there are timer dividers that will produce the desired time resolution. Don't think you can divide by 10 very easily with all the timers. Perhaps 16 MHz would be better than 20. > My plan is to setup some timer/counter to generate an INT after the > first interval, which ISR would set up the nex one and so on. I think > that would work because the minimum period is not lower than 2us so > that should give me 40 clocks for whatever I need to do inside the ISR > to setup for the next one... that's tight but I hope do-able. But if you don't have anything else to do during that time it is more deterministic to poll for the condition than to wait in interrupt. And see above, you might not have to do even that. > Any thoughts on this, before we get to the SPI, please? > > Regarding the SPI, I need to talk to an AD9874 and it's > implementation... looks a bit different, so the question is: is it > do-able? I prefer to not have to bit-bang. If there is no hurry you should drop your bias against bit-banging. On a project my CPU had to be an SPI slave to another. So I put the SPI hardware on that interface and bit banged the DataFlash where my CPU was master. It worked great. But before the project was shipping The Powers That Be decided we would no longer interface to that other SPI thing. I saw no reason to revise the PCB. -- David Kelly N4HHE, dkelly@HiWAAY.net ======================================================================== Whom computers would destroy, they must first drive mad.
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Re: [AVR-Chat] Choosing the right chip for timing resolution, SPI and SSI
2009-08-27 by David Kelly
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