AVR-Chat

Hi there,

Looking at Fig. 15.3 (Pg. 167) and reading the "15.4 Data Modes" paragraph on Pg. 166, I don't see that:

   "Data bits are shifted out and latched in on opposite edges of the SCK signal"

I thought that means that Data Out is valid on MOSI on Rising SCK and Data In is Sampled on MISO on Falling SCK (or the other way)
but it looks like nothing happens on Falling SCK...

I need to know which mode to choose because on the AD9874:
"All data input to the AD9854 is registered on the rising edge of SCLK, and all data is driven out of the AD9854 on the falling edge of SCLK."

What don't I get, please?

Thanks,

Cat


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