AVR-Chat

Hi there,

Looking at Fig. 15.3 (Pg. 167) and reading the "15.4 Data Modes" paragraph on Pg. 166, I don't see that:

   "Data bits are shifted out and latched in on opposite edges of the SCK signal"

I thought that means that Data Out is valid on MOSI on Rising SCK and Data In is Sampled on MISO on Falling SCK (or the other way)
but it looks like nothing happens on Falling SCK...

I need to know which mode to choose because on the AD9874:
"All data input to the AD9854 is registered on the rising edge of SCLK, and all data is driven out of the AD9854 on the falling edge of SCLK."

What don't I get, please?

Thanks,

Cat


[Non-text portions of this message have been removed]

>
> Hi there,
>
> Looking at Fig. 15.3 (Pg. 167) and reading the "15.4 Data Modes" paragraph
> on Pg. 166, I don't see that:
>
>    "Data bits are shifted out and latched in on opposite edges of the SCK
> signal"
>
> I thought that means that Data Out is valid on MOSI on Rising SCK and Data
> In is Sampled on MISO on Falling SCK (or the other way)
> but it looks like nothing happens on Falling SCK...
>
> I need to know which mode to choose because on the AD9874:
> "All data input to the AD9854 is registered on the rising edge of SCLK,
> and all data is driven out of the AD9854 on the falling edge of SCLK."
>
> What don't I get, please?
>
> Thanks,
>
> Cat
>
>
> [Non-text portions of this message have been removed]
>
>

Hi Cat -

It may just be a mixup of words or maybe a misunderstanding of the SPI
process.

On the shifting edge of the clock, data is changing and is NOT valid. It
IS valid about half way through a clock cycle where the opposite edge
occurs. Maybe this is what you were trying to write and it just didn't
quite come out that way.

Give the specs of the AD part, you want to shift the data out from the
micro on the falling edge of SCLK. It will be latched by the AD part on
the rising edge, as described. Since SPI interface is just a fancy shift
register, the input and output shift on the same edge.

Jim Wagner
Oregon Research Electronics

Thank you Jim,

I finally get it : - S
I had mi mind set on a different meaning and couldn't get out of it...

I suppose the inconsistencies in terminology between manufacturers doesn't help either... one registers and one samples; one "drives data out" and one does "setup"... ah maaaaan

Thanks again,

Cat


> To: AVR-Chat@yahoogroups.com
> From: wagnerj@proaxis.com
> Date: Tue, 1 Sep 2009 10:58:53 -0700
> Subject: Re: [AVR-Chat] I don't understand SPI graph in      "ATmega164P/324P/644P" Datasheet (NEW)      8011M�AVR�08/09
> 
> >
> > Hi there,
> >
> > Looking at Fig. 15.3 (Pg. 167) and reading the "15.4 Data Modes" paragraph
> > on Pg. 166, I don't see that:
> >
> >    "Data bits are shifted out and latched in on opposite edges of the SCK
> > signal"
> >
> > I thought that means that Data Out is valid on MOSI on Rising SCK and Data
> > In is Sampled on MISO on Falling SCK (or the other way)
> > but it looks like nothing happens on Falling SCK...
> >
> > I need to know which mode to choose because on the AD9874:
> > "All data input to the AD9854 is registered on the rising edge of SCLK,
> > and all data is driven out of the AD9854 on the falling edge of SCLK."
> >
> > What don't I get, please?
> >
> > Thanks,
> >
> > Cat
> >
> >
> > [Non-text portions of this message have been removed]
> >
> >
> 
> Hi Cat -
> 
> It may just be a mixup of words or maybe a misunderstanding of the SPI
> process.
> 
> On the shifting edge of the clock, data is changing and is NOT valid. It
> IS valid about half way through a clock cycle where the opposite edge
> occurs. Maybe this is what you were trying to write and it just didn't
> quite come out that way.
> 
> Give the specs of the AD part, you want to shift the data out from the
> micro on the falling edge of SCLK. It will be latched by the AD part on
> the rising edge, as described. Since SPI interface is just a fancy shift
> register, the input and output shift on the same edge.
> 
> Jim Wagner
> Oregon Research Electronics
> 
> 
> 
> ------------------------------------
> 
> Yahoo! Groups Links
> 
> 
> 


[Non-text portions of this message have been removed]

Glad I could help.

Jim

>
> Thank you Jim,
>
> I finally get it : - S
> I had mi mind set on a different meaning and couldn't get out of it...
>
> I suppose the inconsistencies in terminology between manufacturers doesn't
> help either... one registers and one samples; one "drives data out" and
> one does "setup"... ah maaaaan
>
> Thanks again,
>
> Cat
>
>
>> To: AVR-Chat@yahoogroups.com
>> From: wagnerj@proaxis.com
>> Date: Tue, 1 Sep 2009 10:58:53 -0700
>> Subject: Re: [AVR-Chat] I don't understand SPI graph in
>> "ATmega164P/324P/644P" Datasheet (NEW)      8011M–AVR–08/09
>>
>> >
>> > Hi there,
>> >
>> > Looking at Fig. 15.3 (Pg. 167) and reading the "15.4 Data Modes"
>> paragraph
>> > on Pg. 166, I don't see that:
>> >
>> >    "Data bits are shifted out and latched in on opposite edges of the
>> SCK
>> > signal"
>> >
>> > I thought that means that Data Out is valid on MOSI on Rising SCK and
>> Data
>> > In is Sampled on MISO on Falling SCK (or the other way)
>> > but it looks like nothing happens on Falling SCK...
>> >
>> > I need to know which mode to choose because on the AD9874:
>> > "All data input to the AD9854 is registered on the rising edge of
>> SCLK,
>> > and all data is driven out of the AD9854 on the falling edge of SCLK."
>> >
>> > What don't I get, please?
>> >
>> > Thanks,
>> >
>> > Cat
>> >
>> >
>> > [Non-text portions of this message have been removed]
>> >
>> >
>>
>> Hi Cat -
>>
>> It may just be a mixup of words or maybe a misunderstanding of the SPI
>> process.
>>
>> On the shifting edge of the clock, data is changing and is NOT valid. It
>> IS valid about half way through a clock cycle where the opposite edge
>> occurs. Maybe this is what you were trying to write and it just didn't
>> quite come out that way.
>>
>> Give the specs of the AD part, you want to shift the data out from the
>> micro on the falling edge of SCLK. It will be latched by the AD part on
>> the rising edge, as described. Since SPI interface is just a fancy shift
>> register, the input and output shift on the same edge.
>>
>> Jim Wagner
>> Oregon Research Electronics
>>
>>
>>
>> ------------------------------------
>>
>> Yahoo! Groups Links
>>
>>
>>
>
>
> [Non-text portions of this message have been removed]
>
>
>
> ------------------------------------
>
> Yahoo! Groups Links
>
>
>
>