Thanks, Graham and George. I already follow these rules with DIP packages, except for the long slits one - I'll keep them shorter in future. And switch to SMT ceramic decoupling cap's (I have been using 0.1 uF tantalum thru-hole). Your mention of hi and lo in parallel brings up something I have wondered about for years. I typically use LP2950 voltage regulators and the data sheet specifies a capacitor on output. For my current design I am using 68 uF. The Vcc power bus from this goes off to the various IC's, each with their own 0.1 uF decoupling capacitor. Is this the situation you are referring to? Steve From: AVR-Chat@yahoogroups.com [mailto:AVR-Chat@yahoogroups.com] On Behalf Of ecros_technology Sent: Saturday, October 24, 2009 8:42 AM To: AVR-Chat@yahoogroups.com Subject: [AVR-Chat] Re: pcb layout of SOIC packages --- In AVR-Chat@yahoogroups.com <mailto:AVR-Chat%40yahoogroups.com> , "Steve Hodge" <steve@...> wrote: > > I'm a newbie to SMT devices and I'm > doing my first pcb layout with them. > With DIP packages I usually arrange > them in a column straddling a Vcc > power bus. Is it OK to do the same > with SOIC packages? VCC routing matters very little if you follow these two important rules. One, connect all grounds with something as close as possible to a continuous plane. Two, decouple each VCC pin as close to the pin as possible with a single, low-inductance ceramic capacitor connected to the ground plane. For SMT designs, most of the ground plane will be on the bottom. Try to route on the top as much as possible (that's where the component pads are) and cross to the bottom as necessary, but don't make long slits in the ground plane. SMT ceramic capacitors will perform better than leaded capacitors for decoupling. Use the smallest size you can handle. 0805 shouldn't be too hard, but I've moved on to 0603 and am starting to use 0402 in dense layouts (but I wouldn't recommend you start there). A good value is 0.1uF. Use the same value everywhere (using a high value and a low value in parallel was once popular but actually makes things worse). Graham. __________ Information from ESET Smart Security, version of virus signature database 4538 (20091024) __________ The message was checked by ESET Smart Security. http://www.eset.com [Non-text portions of this message have been removed]
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RE: [AVR-Chat] Re: pcb layout of SOIC packages
2009-10-24 by Steve Hodge
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