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Re: pcb layout of SOIC packages

2009-10-24 by ecros_technology

--- In AVR-Chat@yahoogroups.com, "Steve Hodge" <steve@...> wrote:
> <snip>
> Your mention of hi and lo in parallel ...
> I am using 68 uF ... goes off to the various
> IC's, each with their own 0.1 uF decoupling
> capacitor.  Is this the situation you are
> referring to?

No.  That's perfect.  The 68 uF isn't really a "decoupling" capacitor.  It is there to a) stabilize the regulator and b) soak up medium-speed changes in load current.  Because it has high parasitic resistance and inductance, it is of very little help in decoupling noise.

Also because of its high parasitic resistance, it doesn't stimulate the problem you get with two different values of ceramic capacitor.

The problem occurs when you have, for example, 0.1 uF and 1 nF decoupling capacitors in parallel.  The (incorrect) thinking behind this is that the 0.1 uF takes care of high frequencies and the 1 nF takes care of very high frequencies.  But, the high frequency performance of modern multi-layer ceramic capacitors is limited by their parasitic inductance, which is a function of the package design, not the capacitance.  So, just use 0.1 uF in a good package.

To understand the problem, draw the circuit diagram of the two parallel capacitors, including their parasitic inductance.  Now consider frequencies at which the larger capacitance is basically a short circuit.  Short it out on your diagram.  What's left?  A parallel tuned circuit!  The smaller capacitance resonates with the combined parasitic inductances, the impedance goes up and the effectiveness for decoupling goes all to hell.

Admittedly, what I'm describing is not an effect you'll run into with miorocontrollers.  However, it pays to get into good habits and why pay for two capacitors when one is actually better?

Graham.

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