AVR-Chat

--- In AVR-Chat@yahoogroups.com, "Steve Hodge" <steve@...> wrote:

> ... the "ADC is optimized for analog
> signals with an output impedance of
> approximately 10 K or less" ... I'm
> wondering if this can be increased to,
> say 15 K or 20 K (or more?), without
> much detectable effect.

You'll be fine.  Any specification with both "approximately" and "less" in it is not to be taken too seriously.  Someone's just discouraging you from having a source impedance an order of magnitude or more above this.  What is probably going on is that the sample / hold capacitor is charged fairly directly from the input, so that with a high source impedance it may not accurately capture the input value by the time the sample period ends.  Maybe you can run the ADC at a speed below maximum, in which case I wouldn't worry at all.

Graham.