On the schematic: - The 7805 wants a ceramic cap (100-330nF) on the input side to reduce the chance of oscillating - The general rule of thumb is one 100nF bypass cap per power pin on each IC - Aref should be connected to a 100nF cap to ground, not Vcc - Stylistic note - you should not have any 4-way connections on the schematic (like either end of R3). They make it hard to catch inadvertant connections or missing ones where nets cross - I would add a 6-pin ISP header, just in case - You may want to add a 120R resistor and jumper across the CAN bus for termination On the board: - Power and ground traces appear too thin. You want them wider to reduce both resistance and inductance - The TVS need a good ground return so any clamping current doesn't get sent through other parts - There's a topside trace under IC5's tab. It is too easy for that to short to the tab - Place an obvious pin-1 indicator by the connectors so you don't have to keep flipping the board over to find the square pad - Some board houses don't like having silk screen on solder pads /mike
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Re: Looking for critique on board layout
2010-11-06 by n1ist
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