AVR-Chat

On May 18, 2012, at 3:39 AM, englsprogeny1 wrote:

> I was thinking about building a simple OS (task scheduler). My thoughts are that the only interrupt that I will service will be a timer used as a 'frame counter/ sync'.
> 
> In each frame (at a specific time) I will check the UART to see if there is anything there.
> 
> Problem here is that none of the ATMegaX processors have a deep FIFO (for UART Rx). This means that if a message is sent to me when I'm not ready to receive I will lose characters.
> 
> The only fix that I can see for this is to have a low baud rate and a fast OS to where I'm checking the Rx buffer faster than a new character can be received (1 character per frame situation).
> 
> Otherwise, I will have to service the UART 'Receive Compete Interrupt'.
> 
> Maybe there is a trick buried in the datasheet that I'm not seeing.
> 
> I want to safely receive (buffer) data seen on the UART Rx wihtout servicing the 'Receive Compete Interrupt'(as if I had a FIFO (maybe 32 characters deep) 
> 
> Any thoughts?
> 
> Hopefully this makes sense to all who read it.
> 
> Many thanks,
> 
> David
> 
> 
Your observation is correct. There are lots of RTOS implementations out there. It should be easy to look at one of them to see how others have done it.

Also, however, think about the numbers. Suppose that the frame sync happens once per millisecond. You would be able to keep up with a sustained 1000 characters per second, At 10 bits per character, (1 start, 8 data, one stop), thats 10Kbaud. Thats not really fast, but its fast enough for a lot of applications. And, 1ms may be a bit slow, because that means 16000 clock cycles per frame for code execution.

Jim Wagner
Oregon Research Electronics





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