AVR-Chat

I was thinking about building a simple OS (task scheduler).  My thoughts are that the only interrupt that I will service will be a timer used as a 'frame counter/ sync'.

In each frame (at a specific time) I will check the UART to see if there is anything there.

Problem here is that none of the ATMegaX processors have a deep FIFO (for UART Rx).  This means that if a message is sent to me when I'm not ready to receive I will lose characters.

The only fix that I can see for this is to have a low baud rate and a fast OS to where I'm checking the Rx buffer faster than a new character can be received (1 character per frame situation).

Otherwise, I will have to service the UART 'Receive Compete Interrupt'.

Maybe there is a trick buried in the datasheet that I'm not seeing.


I want to safely receive (buffer) data seen on the UART Rx wihtout servicing the 'Receive Compete Interrupt'(as if I had a FIFO (maybe 32 characters deep) 

Any thoughts?

Hopefully this makes sense to all who read it.

Many thanks,

David

"englsprogeny1" wrote:

> I want to safely receive (buffer) data seen
> on the UART Rx wihtout servicing the 'Receive
> Compete Interrupt'(as if I had a FIFO ...)
> 
> Any thoughts?

My thought is that it would be much easier to service the Receive Compete Interrupt.  As you are doing something that has been done many times before, I assume you're doing it for fun or the educational experience.  So, perhaps your strange goal with regard to the USART is also a made-up challenge.  But, if it is not, I recommend that you do it the usual way.

Graham Davies
www.ecrostech.com

On May 18, 2012, at 3:39 AM, englsprogeny1 wrote:

> I was thinking about building a simple OS (task scheduler). My thoughts are that the only interrupt that I will service will be a timer used as a 'frame counter/ sync'.
> 
> In each frame (at a specific time) I will check the UART to see if there is anything there.
> 
> Problem here is that none of the ATMegaX processors have a deep FIFO (for UART Rx). This means that if a message is sent to me when I'm not ready to receive I will lose characters.
> 
> The only fix that I can see for this is to have a low baud rate and a fast OS to where I'm checking the Rx buffer faster than a new character can be received (1 character per frame situation).
> 
> Otherwise, I will have to service the UART 'Receive Compete Interrupt'.
> 
> Maybe there is a trick buried in the datasheet that I'm not seeing.
> 
> I want to safely receive (buffer) data seen on the UART Rx wihtout servicing the 'Receive Compete Interrupt'(as if I had a FIFO (maybe 32 characters deep) 
> 
> Any thoughts?
> 
> Hopefully this makes sense to all who read it.
> 
> Many thanks,
> 
> David
> 
> 
Your observation is correct. There are lots of RTOS implementations out there. It should be easy to look at one of them to see how others have done it.

Also, however, think about the numbers. Suppose that the frame sync happens once per millisecond. You would be able to keep up with a sustained 1000 characters per second, At 10 bits per character, (1 start, 8 data, one stop), thats 10Kbaud. Thats not really fast, but its fast enough for a lot of applications. And, 1ms may be a bit slow, because that means 16000 clock cycles per frame for code execution.

Jim Wagner
Oregon Research Electronics





[Non-text portions of this message have been removed]

Hi,
 
Could you use the DMA Controller linked to the UART ?
 
Free-rtos tends to use interrupts to send the data to a port buffer, the buffer is then interrogated by the task.
 
Regards
 


________________________________

From: englsprogeny1 <englsprogeny1@yahoo.com>
To: AVR-Chat@yahoogroups.com 
Sent: Friday, 18 May 2012, 11:39
Subject: [AVR-Chat] USART Interrupts


  
I was thinking about building a simple OS (task scheduler). My thoughts are that the only interrupt that I will service will be a timer used as a 'frame counter/ sync'.

In each frame (at a specific time) I will check the UART to see if there is anything there.

Problem here is that none of the ATMegaX processors have a deep FIFO (for UART Rx). This means that if a message is sent to me when I'm not ready to receive I will lose characters.

The only fix that I can see for this is to have a low baud rate and a fast OS to where I'm checking the Rx buffer faster than a new character can be received (1 character per frame situation).

Otherwise, I will have to service the UART 'Receive Compete Interrupt'.

Maybe there is a trick buried in the datasheet that I'm not seeing.

I want to safely receive (buffer) data seen on the UART Rx wihtout servicing the 'Receive Compete Interrupt'(as if I had a FIFO (maybe 32 characters deep) 

Any thoughts?

Hopefully this makes sense to all who read it.

Many thanks,

David




[Non-text portions of this message have been removed]

This is somewhat of an aside.   I just finished porting my USART ISR's from
mega to xmega.   They only use the Receive Complete (RXC) and Transmit
Complete (TXC) interrupts.  I've always been curious as to when one would
use the "Data Register Empty" (DRE) interrupt.  Can somebody give a brief
reason when and why to use this one?  Thanks, Steve

From: AVR-Chat@yahoogroups.com [mailto:AVR-Chat@yahoogroups.com] On Behalf
Of bayramdavies
Sent: Friday, May 18, 2012 6:20 AM
To: AVR-Chat@yahoogroups.com
Subject: [AVR-Chat] Re: USART Interrupts

 

  

"englsprogeny1" wrote:

> I want to safely receive (buffer) data seen
> on the UART Rx wihtout servicing the 'Receive
> Compete Interrupt'(as if I had a FIFO ...)
> 
> Any thoughts?

My thought is that it would be much easier to service the Receive Compete
Interrupt. As you are doing something that has been done many times before,
I assume you're doing it for fun or the educational experience. So, perhaps
your strange goal with regard to the USART is also a made-up challenge. But,
if it is not, I recommend that you do it the usual way.

Graham Davies
www.ecrostech.com





[Non-text portions of this message have been removed]

On May 18, 2012, at 8:47 AM, Steven Hodge wrote:

> This is somewhat of an aside.   I just finished porting my USART ISR's from
> mega to xmega.   They only use the Receive Complete (RXC) and Transmit
> Complete (TXC) interrupts.  I've always been curious as to when one would
> use the "Data Register Empty" (DRE) interrupt.  Can somebody give a brief
> reason when and why to use this one?  Thanks, Steve

The USART transmit is "double buffered" (UARTs were not always) with a data buffer and a serial buffer. DRE indicates when data has moved into the shift register. TXC indicates when the shift register is empty. DRE gives you one extra character interval to get the next character into place before a gap appears on the TXD wire.

--
David Kelly N4HHE, dkelly@HiWAAY.net
============================================================
Whom computers would destroy, they must first drive mad.

I think if you have a TX buffer you use that interrupt to send the next char in the buffer (if not empty).

Cat

> To: AVR-Chat@yahoogroups.com
> From: steve@terrafirma.us
> Date: Fri, 18 May 2012 06:47:48 -0700
> Subject: RE: [AVR-Chat] Re: USART Interrupts
> 
> This is somewhat of an aside.   I just finished porting my USART ISR's from
> mega to xmega.   They only use the Receive Complete (RXC) and Transmit
> Complete (TXC) interrupts.  I've always been curious as to when one would
> use the "Data Register Empty" (DRE) interrupt.  Can somebody give a brief
> reason when and why to use this one?  Thanks, Steve
> 
>  

 		 	   		  

[Non-text portions of this message have been removed]

Sent from an iPhone, but is it mine?

On May 18, 2012, at 6:47 AM, "Steven Hodge" <steve@terrafirma.us> wrote:

> This is somewhat of an aside. I just finished porting my USART ISR's from
> mega to xmega. They only use the Receive Complete (RXC) and Transmit
> Complete (TXC) interrupts. I've always been curious as to when one would
> use the "Data Register Empty" (DRE) interrupt. Can somebody give a brief
> reason when and why to use this one? Thanks, Steve
Normally you use the DRE for sending out serial data. This gives you the highest data rate. Using TxC adds a short space between characters. 

In my RS-485 code I use DRE to send the data then TxC to switch the bus transceiver to receive when the packet has been sent. 

One important point is that DRE will generate an interrupt any time the buffer is empty. So you need to disable the DRE interrupt enable bit when you have sent the last byte. Otherwise it will continue to call the service routine. 
> 


[Non-text portions of this message have been removed]

Thanks a lot for everyone's input on the DRE interrupt.   I'll probably use
it at some point.   Steve

From: AVR-Chat@yahoogroups.com [mailto:AVR-Chat@yahoogroups.com] On Behalf
Of Clark Martin
Sent: Friday, May 18, 2012 9:01 AM
To: AVR-Chat@yahoogroups.com
Subject: Re: [AVR-Chat] Re: USART Interrupts

 

  



Sent from an iPhone, but is it mine?

On May 18, 2012, at 6:47 AM, "Steven Hodge" <steve@terrafirma.us
<mailto:steve%40terrafirma.us> > wrote:

> This is somewhat of an aside. I just finished porting my USART ISR's from
> mega to xmega. They only use the Receive Complete (RXC) and Transmit
> Complete (TXC) interrupts. I've always been curious as to when one would
> use the "Data Register Empty" (DRE) interrupt. Can somebody give a brief
> reason when and why to use this one? Thanks, Steve
Normally you use the DRE for sending out serial data. This gives you the
highest data rate. Using TxC adds a short space between characters. 

In my RS-485 code I use DRE to send the data then TxC to switch the bus
transceiver to receive when the packet has been sent. 

One important point is that DRE will generate an interrupt any time the
buffer is empty. So you need to disable the DRE interrupt enable bit when
you have sent the last byte. Otherwise it will continue to call the service
routine. 
> 

[Non-text portions of this message have been removed]





[Non-text portions of this message have been removed]