AVR-Chat

>
>Well, a lot of places, actually. Articles on the Web (such as the one 
>mentioned in this thread), in technical magazines and presentations 
>by vendors. I've also directly observed the difference in processors 
>I've worked with.

So my tiny-11 is CISC, because it can operate directly on all the ram it can address?
:)

There's a lot of confusion out there, caused by marketers that want their processor to look a certain way to their customer base. 


>> "RISC" and "CISC" are marketing distinctions.
>This is also true, but not very interesting.

Well, I think it's the primary distinction..
It started as a marketing thing to make a processor with a limited (but faster) instruction set look more powerful than a processor with a more comprehensive (but slower) instruction set, and had nothing to do with where the memory was located.


>Thank you for pointing out my error in such a kind way.

:)

> However, I wan't talking about the Z8, I was talking about the Z8 Encore!

Major difference.

> Only 16 memory locations are accessible at any one time as registers. 

Hmm.. Aren't the AVR registers mappable as RAM as well?
I never use them that way, so I don't remember offhand.

>The  rest must be addressed as memory using one of an intimidatingly large 
>number of addressing modes.

The Z8 is good with modes. LOADS of modes. 

> However, once you've addressed a memory location, you can do things to it directly without loading to a register, operating and storing the result.
>
>So, it is CISC.
>Bing! True.

I disagree. Rich Instruction Set, and Complex Instruction Set, make no mention of how ram is accessed.