i agree with Mr Davies. a RISC computer involves register-to-register operation while a CISC involves lots of memory access. that is why the AVR has 32 registers in its register file since a RISC computer requires atleast 32 registers. the CISC however involves memory access. that is why we lots of different addressing modes in a CISC than in a RISC.
also, from what i've learned in class, a RISC computer has a definite number of op-codes per instruction, except for memory related instructions. the AVR has 2 bytes of op-codes for simple instructions, as what i've read from the .lst file.
A CISC computer don't have a definite number of op-code per instruction. some may only have 4 bytes, while some have 5 or 6. this is what i've found in the Z-80 uP.
the speed of processing a single byte of op-code however goes with the microprogram routines inside the CPU itself.
David VanHorn <dvanhorn@cedar.net> wrote:
At 08:49 AM 7/28/2004, Graham Davies wrote:
>--- In AVR-Chat@yahoogroups.com, "Astria Nur Irfansyah"
><irfansyah@t...> wrote:
>
>> ... AVRs instruction set
>> is not so reduced ...
>
>These days, what distinguishes RISC and CISC is not so much the size
>of the instruction set but whether you can perform operations
>directly on memory. In the AVR, you have to load data from memory to
>a register, operate on it and write it back, therefore it is RISC.
Where did you get that idea?
"RISC" and "CISC" are marketing distinctions.
The limit case of RISC is a processor with one infinitely fast instruction called "NOP". Kind of useless, but really fast!
The more instructions a processor supports, the more you can get done, in a finite number of instructions. Usually, the CISC processor is slower per cycle than the RISC processor, but this is not always the case. In fact, the Z8 was running at 12 clocks per instruction, the PIC four, and the AVR usually one.
Atmel has some cases of what I would call BS-Ops, like the SBI/R and CBI/R, (really just AND and OR operations) and CLR, which is really just LDI X,0. These happen in the assembler though, they aren't implemented as separate instructions in the processor.
>(There are exceptions for built-in peripherals.) In the ZiLOG Z8
>Encore! (for example) you can operate directly on memory,
True All on-chip ram is registers. I don't remember if it handles off-chip ram this way, but I doubt it.
> so it is CISC.
BZZZT False.
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