AVR-Chat

At 09:59 PM 13/01/04 -0500, David VanHorn wrote:
>What am I missing here?
>

Don't know but here's what I do with the mega8 SPI in one project.

setup
.....
	ldi	r16,0b11101110		;PORTB B0=icp and B4=Miso as inputs
	out	DDRB,r16		;all other outputs
.....
;Set up SPI, LSB first, Master, clock idle high, phase=1, clock fck/64
	ldi	r17,(1<<SPE)|(1<<DORD)|(1<<MSTR)|(1<<CPOL)|(1<<CPHA)|(1<<SPR0)|(1<<SPR1)
	out	SPCR,r17
.....
;Sends spireg out serially. Clock is ACTIVE LOW, IDLING HIGH.
;(Mode 3) Bits are shifted out LSB FIRST.
spi_out:
; Start transmission of data (spireg)
	cbi	portb,SS	;Clear /SS pin
	out	SPDR,spireg
; Wait for transmission complete
Wait4spif:
	sbis	SPSR,SPIF
	rjmp	Wait4spif
	sbi	portb,SS	;Set /SS pin
	ret	
.....

It may not help but sometimes it's the things that are overlooked
that do the trick....as you well know.

Regards

John Samperi

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