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Re: [AVR-Chat] M8 SPI

2004-01-14 by John Samperi

At 02:43 AM 14/01/04 -0500, you wrote:
>>        cbi     portb,SS        ;Clear /SS pin
>
>This one, I don't understand. 
>It looks like you're setting up as a slave?

The master is lowering the SS (Slave Select or enable)
pin to let the slave know that data is coming. Of course
one could leave SS always low if there is only one
slave attached to the master in mode 3.

>;Set up SPI, LSB first, Master, clock idle high, phase=1, clock fck/64
>        ldi
r17,(1<<SPE)|(1<<DORD)|(1<<MSTR)|(1<<CPOL)|(1<<CPHA)|(1<<SPR0)|(1<<SPR1)
>        out     SPCR,r17

>Where it matters, we are doing the same thing, SPI enabled, and Master are
"1" on mine, the rest zero. 

So you are not using mode 3 as CPHA and CPOL are zero. (have deleted your
previous email)

From the Motorola HC11 data book:
****
When CPHA equals 0, the SS line must be negated and reasserted
between each successive serial byte. Also, if the slave writes data to the
SPI data register (SPDR) while SS is low, a write collision error results.

When CPHA equals 1, the SS line can remain low between successive
transfers.
*****
The Mega8 manual doesn't seem to explain this in the section
SS Pin Functionality, but I suspect that something similar may
be happening. It does however mention a few things about the
SS pin in master mode. May want to have a fresh look at it.

>>        sbi     portb,SS        ;Set /SS pin
>>        ret     

Disable slave at end of transmission.




Regards

John Samperi

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