AVR-Chat

Here's what I don't get.  One of the most 
important uses of SRAM and parallel EEPROM
and Flash is as microcontroller memory.  If
you'll look over the datasheets of MOST of 
your simple MCU's you'll find something kind
of important.  Almost all of them multiplex
8 bits of the address with the data lines.

I've taken apart lots of equipment and I 
see that even manufacturers get stuck with
the same BS that we do.  You'll usually 
find a latch...interfacing to that memory.

CONSIDERING that the amount of space it would
take to replicate that same latch on the die
of a SRAM chip is smaller than a grain of 
salt...why the hell hasn't someone pulled 
their heads out of their posteriors long 
enough to see that there's a very real NEED
for a parallel SRAM, Flash and EEPROM with
a multiplexed data/address bus???

Not only would this eliminate a whole chip
from many projects and commercial circuit
boards...it would cut down the size of the
RAM chip as well.  One could easily fit
up to 128k of SRAM on a 24pin chip
VCC, VSS, ALE, DA0-7, A8-15 and one for
either chip enable (on 64k chips) or bank
select on 128k chips.

This is of course completely ignoring the
idea of multiplexing all data and address
lines (one of those would only have 16
pins)

Ok, finished ranting