AVR-Chat

Here's what I don't get.  One of the most 
important uses of SRAM and parallel EEPROM
and Flash is as microcontroller memory.  If
you'll look over the datasheets of MOST of 
your simple MCU's you'll find something kind
of important.  Almost all of them multiplex
8 bits of the address with the data lines.

I've taken apart lots of equipment and I 
see that even manufacturers get stuck with
the same BS that we do.  You'll usually 
find a latch...interfacing to that memory.

CONSIDERING that the amount of space it would
take to replicate that same latch on the die
of a SRAM chip is smaller than a grain of 
salt...why the hell hasn't someone pulled 
their heads out of their posteriors long 
enough to see that there's a very real NEED
for a parallel SRAM, Flash and EEPROM with
a multiplexed data/address bus???

Not only would this eliminate a whole chip
from many projects and commercial circuit
boards...it would cut down the size of the
RAM chip as well.  One could easily fit
up to 128k of SRAM on a 24pin chip
VCC, VSS, ALE, DA0-7, A8-15 and one for
either chip enable (on 64k chips) or bank
select on 128k chips.

This is of course completely ignoring the
idea of multiplexing all data and address
lines (one of those would only have 16
pins)

Ok, finished ranting

poitsplace wrote:

[snip]

> CONSIDERING that the amount of space it would
> take to replicate that same latch on the die
> of a SRAM chip is smaller than a grain of
> salt...why the hell hasn't someone pulled
> their heads out of their posteriors long
> enough to see that there's a very real NEED
> for a parallel SRAM, Flash and EEPROM with
> a multiplexed data/address bus???

Of course it could be done, much better than that, they could include some
non-volatile protection, incorporating a NVBattery input pin, and more,
include a real time clock in there, and having a communication protocol and
available electronics, they could include a thermal sensor, cost by cost it
could be very cheap since nothing fancy was implemented.  But it would
require 3 or 4 communication cycles to input data, addresses, get data back,
etc.  Then, if processor cycles is not that much important nowadays with the
fast AVR available, then why not take all the parallel thing away and
implement everything in a single wire?  The processor who does 4 cycles to
read something could do 25 cycles in fast clock and space will be saved more
and more. Perhaps this is they invented SPI memories...

I agree with you.  Latched SRAM would be a real nice thing. Instead to use
/OE and /CE they could switch it to /CE1, /CE2, combination of those would
select;  00 = Address Latch1, 01 = Address Latch2, 02 = Data Latch Read, 03
= Data Latch Write. Thats it.

Wagner.


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--- In AVR-Chat@yahoogroups.com, "poitsplace" <lmburt@e...> wrote:
> [...] 
> CONSIDERING that the amount of space it would
> take to replicate that same latch on the die
> of a SRAM chip is smaller than a grain of 
> salt...why the hell hasn't someone pulled 
> their heads out of their posteriors long 
> enough to see that there's a very real NEED
> for a parallel SRAM, Flash and EEPROM with
> a multiplexed data/address bus???
> 
> Not only would this eliminate a whole chip
> from many projects and commercial circuit
> boards...

If you are very limited in board space (and so desperate to pay a 
prize for it) you might want to take a look at PSDs:
http://www.st.com/stonline/products/families/memories/psm/psd4000.htm

Stefan

MY main point was that since a high percentage
of the chips are being used in this way (probably
MOST of them) it's kind of crazy that it's not
readily available.

--- In AVR-Chat@yahoogroups.com, "Stefan Wimmer" <yahoo@w...> wrote:
> --- In AVR-Chat@yahoogroups.com, "poitsplace" <lmburt@e...> wrote:
> > [...] 
> > CONSIDERING that the amount of space it would
> > take to replicate that same latch on the die
> > of a SRAM chip is smaller than a grain of 
> > salt...why the hell hasn't someone pulled 
> > their heads out of their posteriors long 
> > enough to see that there's a very real NEED
> > for a parallel SRAM, Flash and EEPROM with
> > a multiplexed data/address bus???
> > 
> > Not only would this eliminate a whole chip
> > from many projects and commercial circuit
> > boards...
> 
> If you are very limited in board space (and so desperate to pay a 
> prize for it) you might want to take a look at PSDs:
> 
http://www.st.com/stonline/products/families/memories/psm/psd4000.htm
> 
> Stefan

Finally said the heck with it and wrote
every SRAM manufacturer I could find an 
address for.


--- In AVR-Chat@yahoogroups.com, "poitsplace" <lmburt@e...> wrote:

> Here's what I don't get.  One of the most 
> important uses of SRAM and parallel EEPROM
> and Flash is as microcontroller memory.  If
> you'll look over the datasheets of MOST of 
> your simple MCU's you'll find something kind
> of important.  Almost all of them multiplex
> 8 bits of the address with the data lines.
> 
> I've taken apart lots of equipment and I 
> see that even manufacturers get stuck with
> the same BS that we do.  You'll usually 
> find a latch...interfacing to that memory.
> 
> CONSIDERING that the amount of space it would
> take to replicate that same latch on the die
> of a SRAM chip is smaller than a grain of 
> salt...why the hell hasn't someone pulled 
> their heads out of their posteriors long 
> enough to see that there's a very real NEED
> for a parallel SRAM, Flash and EEPROM with
> a multiplexed data/address bus???
> 
> Not only would this eliminate a whole chip
> from many projects and commercial circuit
> boards...it would cut down the size of the
> RAM chip as well.  One could easily fit
> up to 128k of SRAM on a 24pin chip
> VCC, VSS, ALE, DA0-7, A8-15 and one for
> either chip enable (on 64k chips) or bank
> select on 128k chips.
> 
> This is of course completely ignoring the
> idea of multiplexing all data and address
> lines (one of those would only have 16
> pins)
> 
> Ok, finished ranting