On Apr 26, 2006, at 12:03 PM, Peter Harrison wrote: > Hi > > I have an optical sensor. It triggers an emitter and reads a response > from a photodiode and amplifier. after firing the emitter, I wait > until > the amplifier has had time to reach a stable output - say 5us - then I > initiate an ADC conversion. > > Now, If I turn off the emitter too soon, the ADC result is > decreased so > my question is: How long should I keep the signal present at the ADC > input to allow the internal sample and hold capacitor to charge? > > According to the (ATMEGA32) datasheet, the S/H capacitor has a > value of > 14pF but the series resistance of the multiplexer is shown as > 1..100kOhm. This seems a bit of a large range. Time constants could be > up to 1.4us requiring that I wait as long as 7us or so to charge the > capacitor. The source impedance is an op-amp output so it should not > have any effect to speak of. The sheet also describes the sampling > time > as negligible. Seems like a new, optimistic definition of the word > to me. > The 7usec is not out of line, considering that the sample/hold is sampling until 1.5 sample clocks after asserting ADSC (which is, at best, 7.5usec given that 200KHz is the max clock for 10 bit conversions). > My code seems to need to wait at least 1us before turning off the > emitter. As I need to perform 5k conversions per second, I could do > without wasting all that time in the timer interrupt waiting for the > signal to settle. I already have to arrange that on a timer tick, I > collect the previous result and then fire off another conversion. > Have you considered "free-running" mode? > Have I got it right and this is just how it works, or have I missed > something? Is the switch resistance really that variable? -- Ned Konz MetaMagix embedded consulting MetaMagix@gmail.com
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Re: [AVR-Chat] ADC sample time
2006-04-27 by Ned Konz
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