Doepfer

Ok,

I think, I've got it:

The core is an RS-Flipflop, which is controlled at SET by the halftime
clock (dived by 2) and by the the Stop trigger at RESET. The Q-Out
controls an AND which enables the Clock:

Clock---------+------------------\
               |                  |
Start---Reset-x/2                \--AND
               |       ......        AND----Clock to seq-counter
               \-------.S  Q.--------AND
Stop------------------.R -Q.
                       ......

Should work like that:
"Stop" resets the Q to low. This disables the Clock at the Sequencer
counter. Start resets the divider which diveds the clock. So the divided
clock is low. At the second clock pulse the divided clock becomes high
-> the high activates set, which enables the clok in the AND.

Florian


Florian Anwander wrote:

> Hi Dieter
> 
> we do not want to have this, because a reset while playmode would show 
> the same behaviour.
> 
> This "wait for second step"-behaviour should only be shown if the reset 
> comes while stop mode or at the didentical moment with the 
> start-trigger. I think this requires some RS-Flipflop work...
> 
> Florian
> 
> 
> 
> hardware@doepfer.de wrote:
> 
>>> there are counter ICs that after receiving a reset pulse will wait
>>> with incrementing their state untill they receive the next clock pulse .
>>
>>
>>
>> Denis,
>>
>> very interesting. Can you tell me the name of this counter circuit. 
>> Maybe we
>> could do a redesign of the A-155 controller board. Now a CD4024 is 
>> used as
>> counter.
>>
>> Dieter
>>
>>
>>
>>  
>> Yahoo! Groups Links
>>
>>
>>
> 
> 

-- 
Florian Anwander                  |ConSol
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