Hello Neil Thanks for the hint. I did some further experiments the last hour, and can confirm, that the CP1 is more stable on a only slightly varying master frequency, but it would not cover a wider frequency range (more than an octave) of the input signal. For varying frequencies I get the best results with CP3. In the range of the input signal between 80 and 400Hz I get up to two and a half octaves - but for the Din-Sync clock multiplication I will have input signals between 10 Hz and 100Hz. I tried with various filters (esp. the slewlimiter), but I do not get a satisfying range with this low input frequency. I can make it track fine, if I send an additional control voltage to the PLL's VCO and to the VC-slewlimiter, that corresponds to the frequency of the input signal. But this will not be available in the case of the DIN-Sync multiplication. I think for my DIY project I will work with a two stage approach. Part 1 will be counter based F/V converter, which provides a rough control voltage. Part 2 will be the PLL that does the fine tuning. Nevertheless if anyone can provide reliable settings for low frequency syncing with an wide range, any help is appreciated. > you are looking to do a x40 multiplication which using the A160/161 is not going to work > (sorry you clearly know this already), Yes ;-) It won't work only the 160/161 or with a standard 160/161 . But there are several approaches to achieve it: The first is: use logic gates, that read decimal 41 = binary 101001 from the output of 160 and send the output to the reset. The second is: take the 1/8 signal from the A-160 and trigger with it the A-161 and use the step 6 as reset. This requires a modified A-161 that has been extended with a separate clock input. But in fact, I want to use the A-100 system experiment only with the PLL. Therefor it is not necessary to have the true division factor. The final device will be a custommade standalone unit, where the divider is made from a CD4520 and two ANDs. Florian Am 23.04.2015 um 08:56 schrieb Neil Kagan blinkenlicht@yahoo.com [Doepfer_a100]: > I don't know if there is an 'ideal' setup. Certainly CP1 seems more > stable than the other two, as it locks at harmonics. I think you might > find that it is going to be a process of just trying things until it > works... One thing I did notice is that you are looking to do a x40 > multiplication which using the A160/161 is not going to work (sorry > you clearly know this already), so would the VC frequency divider be a > better option?
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Re: [Doepfer_a100] Experiences with the A196 PLL
2015-04-23 by Florian Anwander
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