Lpc2000

--- In lpc2000@yahoogroups.com, David Hawkins <dwh@o...> wrote:
>
> Hi all,
> 
> I have an application where I need to emulate a synchronous
> serial interface to a microVAX (yeah really!).
> 

> with the byte SPI interface, the 21-bit transaction would
> consist of 2 complete bytes and then a 5-bit byte to give
> 21-bits. I'd probably count the clocks and then deassert
> SSEL after bit 21 (which will cause an SPI abort to be
> asserted, but that should be ok).
> 

I don't know of any 21-bit memory devices.

So 24 bits is just as good.

> The SPI transmitter is not buffered in any way, so my
> question relates to the transition between bytes,
> I would get an interrupt when the first byte is
> done, and would use that to write the second byte,
> and again for the third byte. My concern has to do with
> the bit timing between bytes.
> 

SPI transfers are 8-clocks then an interrupt. ( if enabled)
If there is ony 5 clocks, how does the receiver know that byte is
valid. And where will the interrupt happen?

If the clock is not running, then you can take as long as you want
before the next byte. The slave SPI port can not force the master to
do anything. It will just have to wait.

> I'll write some code and figure all this out, but
> just thought I'd post this to see if anyone had
> used the SPI port for multiple-byte transitions
> in slave mode to hear their experience.
> 
> I'm still waiting on documentation for the microVAX
> timing. If its really slow, then I can just use
> an IRQ line on the clock from the microVAX and
> write the data to an I/O pin. Using the SPI port
> as a shift-register does seem nice and elegant
> though.
> 
> And of course, if the SPI port can not be used,
> I'll just do the obvious and put a 21-bit shift
> register on the adapter, or an FPGA and have
> extra logic for later.

The SPI port is just fine. Unless you need an FPGA ?


> 
> Cheers
> Dave
>