Lpc2000

> So the question still remains as to what is the bit
> timing of a multi-byte SPI transaction with regard to;
> 
>   * bit 7 (the last bit of the first byte) and bit 8
>     (the first bit of the second byte)
> 
>   * bit 15 (the last bit of the second byte) and bit 16
>     (the first bit of the third byte)
> 
> i.e., I'm unsure about what happens with the data on the
> SPI slave output pin during the following sequence;
> 
>    - last bit is present on the slave-out pin
>    - SPI interrupt occurs
>    - new data is written to the SPI transmit register
> 
> now, if the SPI transmit register is directly connected
> to the SPI slave out pin, the data on the slave output
> will change when the transmit register is written to.
> If its not directly connected and in fact there is a
> 1-bit slave output register, then the data will stay
> until the next clock edge from the microVAX master comes
> along.

 From p180 of the User Manual:

   The SPI data register is used to provide the transmit and
   receive data bytes. An internal shift register in the SPI
   block logic is used for the actual transmission and
   reception of the serial data. Data is written to the SPI
   data register for the transmit case. There is no buffer
   between the data register and the internal shift register.
   A write to the data register goes directly into the internal
   shift register. Therefore, data should only be written to
   this register when a transmit is not currently in progress.
   Read data is buffered. When a transfer is complete, the
   receive data is transferred to a single byte data buffer,
   where it is later read. A read of the SPI data register
   returns the value of the read data buffer.

So it would appear that ANY write to the transmit register
will cause a transition on the slave-output pin as soon
as the write occurs. This would be ok if you knew that
the external SPI master had already read that bit, so it
all depends now on when the SPI transmit complete IRQ fires.
Is it just after that last bit is written to the register,
or just after the clock edge that would have read that
bit? If the IRQ fires when the last clock occurs,
then the IRQ processing time plus write to the
transmit register must occur within the setup time
of the next external master clock.

But as soon as you have to process this case, you can
solve the same problem by tying the external master
clock to an external IRQ line, and driving the data
from an I/O pin (albeit now the LPC processes an
IRQ per bit rather an an IRQ per byte).

Dave