Lpc2000

(sorry, some more thinking out loud)

 > This would be ok if you knew that
> the external SPI master had already read that bit, so it
> all depends now on when the SPI transmit complete IRQ fires.
> Is it just after that last bit is written to the register,
> or just after the clock edge that would have read that
> bit? If the IRQ fires when the last clock occurs,
> then the IRQ processing time plus write to the
> transmit register must occur within the setup time
> of the next external master clock.
> 
> But as soon as you have to process this case, you can
> solve the same problem by tying the external master
> clock to an external IRQ line, and driving the data
> from an I/O pin (albeit now the LPC processes an
> IRQ per bit rather an an IRQ per byte).

p181 of the User Manual:

    The SPIF bit will be set after the last sampling
    clock edge of the SPI data transfer

So in slave mode, the IRQ fires after the last 'sampling'
clock edge. Which implies that the external master has
read the bit.

This SPI controller implementation seems 'weak' for the
case of implementing multiple-byte slave transfers.
The weakness being that the external master period must
be longer than the time taken to process an SPI
IRQ interrupt and load the next byte into the
transmit register.

If there had been a double buffered register on the
SPI transmit port, then the next byte could be loaded
while the current byte was being transmitted, and
hence the effect of the clock period of the external
master would be reduced to effecting byte timing
not bit timing.

Do any of the other LPC parts use double buffers on
their SPI transmit ports?

Cheers
Dave