At 03:44 AM 2/19/04 +1100, you wrote:
>If someone can clarify a bit better what the hell the deal is exactly with
>the TX FIFO,
>I'd be grateful. I've googled around on 16C550 till I'm silly, but not
>much luck
>finding a description how exactly the TX FIFO works. Is it a FIFO between
>THR and
>the actual Shift register ? That's my interpretation, but then you still
>get the same
>amount of TX interrupts anyway, just that they're spaced together in time
>a lot more,
>with more gap in between.
>I don't see the point, or maybe I just don't get it. The RX, fair enough,
>that is great
>having a FIFO there.
I wanted to check the documentation before I commented (to refresh my
memory on the FIFO). You get a lot of the same benefits you get from a RX
FIFO. When you get an interrupt you can sit in a loop and stuff the FIFO
full before returning. That nicely lowers the interrupt overhead by a
factor of 15 or 16. On the down side the main service body will take
longer, maybe not a full 15x longer but longer so that each individual
interrupt may be longer and increase your latency. If you just put in one
character and exit the interrupt it will probably act just as you say.
" 'Freedom' has no meaning of itself. There are always restrictions,
be they legal, genetic, or physical. If you don't believe me, try to
chew a radio signal. "
Kelvin Throop, IIIMessage
Re: [lpc2000] UART TX FIFO and INTs problem
2004-02-18 by Robert Adsett
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