Lpc2000

gen_4p

>> > - during operation update user data in RAM only
>>
>> I'd store the RAM copy from time to time in the back-ground
>>
>
> Unfortunately this is not going to work for me (so i'd love to...).
> The system in design is a sound development system with 10 ms cycle,
> and max I can miss is one cycle once in a while. So there is no way I
> can spend 400ms for sector erasing and backing data up.

Isn't sector erasing self-timed ? Maybe you need to do it manualy, not via
IAP ?

>> > - on power-down use VDD delay to store RAM user data array in on-
>> >   chip flash
>
> Also I would like to make sure again. According to the ee_demo,
> though code is executed from the main flash, all operations on a
> flash writing are done through the bootloader/IAP. Is it right?
>
> And I do have my doubts on implementing data storage in on-chip flash
> (from development efforts point of view). SPI external flash for $1
> will do the same and, probably, with a lot less efforts.

External flash or EEPROM has IMHO a lot of advantages though the 
disadvantage
of having one chip more.

Pros:
- up to 1 million times erasable (FRAM even more, but more expensive)
- erasing will not disturb the LPCs program flow. IAP means IIRC the 
interrupts are locked because you can not run from flash while erasing.
- there are EEPROM with a large buffer, so writing is only the SPI speed.


-- 
42Bastian Schick