Lpc2000

Hi,
how effective is it to store user data (which can be updated 
relatively frequently) on lpc2138/48?
User data size is about 2K.
Data should be stored/updated within max 2ms.
Data is going to be loaded to RAM on power-up and operated from RAM.
 
As far as I understand, I have the following options:
1. Use external nonvolatile data memory (like spi flash, preferably 
with byte write capability) and update data in RAM and external flash 
on a fly.
2. Update data only in RAM. On power-down create sufficient VDD delay 
and store the whole RAM user data array to the on-chip flash. Not 
sure how long storing of 2K of data will take. And I believe that 
according to one of the previous discussions I can write data to the 
on-chip flash providing interrupts are disabled (?)
3. Update data in RAM and in on-chip flash on a fly. As far as I 
understand, there is no byte-write provision for flash in lpc, so I 
will need to save a page - 256 bytes. The question here is, of 
coarse, time to store a page, and, second - flash endurance. How many 
times can I write to the flash (I couldn't find information on that)?

Will appreciate advice and considerations.

Gennady

Hi Gennady,

> 2. Update data only in RAM. On power-down create sufficient VDD delay
> and store the whole RAM user data array to the on-chip flash. Not
> sure how long storing of 2K of data will take. And I believe that
> according to one of the previous discussions I can write data to the
> on-chip flash providing interrupts are disabled (?)

There are some notes when using IAP on page 294 of the LPC214x user manual.
 
> 3. Update data in RAM and in on-chip flash on a fly. As far as I
> understand, there is no byte-write provision for flash in lpc, so I
> will need to save a page - 256 bytes. The question here is, of
> coarse, time to store a page, and, second - flash endurance. How many
> times can I write to the flash (I couldn't find information on that)?

Page 6 of the LPC214x user manual:
" The LPC2141/2/4/6/8 Flash memory provides minimum of 100,000 erase/write
cycles and 20 years of data-retention."

This is a demo posted by Phillips apps that you might be interested in:
http://groups.yahoo.com/group/lpc2000/files/EE_demo.zip 


Joel

Thanks a lot Joel,

well, I missed those 400ms for sector erase - bad news for me.
Then, may be I can use another way:
- on power-up load user data to RAM (also duplicating in external
  serial flash ?)
- erase user data sectors in on-chip flash. At this point time to
  erase is not that critical
- during operation update user data in RAM only
- on power-down use VDD delay to store RAM user data array in on-chip
  flash

Gennady

> > 2. Update data only in RAM. On power-down create sufficient VDD 
delay
> > and store the whole RAM user data array to the on-chip flash. Not
> > sure how long storing of 2K of data will take. And I believe that
> > according to one of the previous discussions I can write data to 
the
> > on-chip flash providing interrupts are disabled (?)
> 
> There are some notes when using IAP on page 294 of the LPC214x user 
manual.
>  
> > 3. Update data in RAM and in on-chip flash on a fly. As far as I
> > understand, there is no byte-write provision for flash in lpc, so 
I
> > will need to save a page - 256 bytes. The question here is, of
> > coarse, time to store a page, and, second - flash endurance. How 
many
> > times can I write to the flash (I couldn't find information on 
that)?
> 
> Page 6 of the LPC214x user manual:
> " The LPC2141/2/4/6/8 Flash memory provides minimum of 100,000 
erase/write
> cycles and 20 years of data-retention."
> 
> This is a demo posted by Phillips apps that you might be interested 
in:

> http://groups.yahoo.com/group/lpc2000/files/EE_demo.zip 
> 
> 
> Joel
>

gen_4p <gennadyp@...> schrieb am Tue, 22 Nov 2005 14:29:55 -0000:

> Thanks a lot Joel,
>
> well, I missed those 400ms for sector erase - bad news for me.
> Then, may be I can use another way:
> - on power-up load user data to RAM (also duplicating in external
>   serial flash ?)
> - erase user data sectors in on-chip flash. At this point time to
>   erase is not that critical

I'd use two sectors to have in case of valid copy in case of a power-down
during erase.

> - during operation update user data in RAM only

I'd store the RAM copy from time to time in the back-ground


-- 
42Bastian Schick

> well, I missed those 400ms for sector erase - bad news for me.
> Then, may be I can use another way:
> - on power-up load user data to RAM (also duplicating in external
>   serial flash ?)

This would just require a modification to your CRT init code. 

> - erase user data sectors in on-chip flash. At this point time to
>   erase is not that critical
> - during operation update user data in RAM only
> - on power-down use VDD delay to store RAM user data array in on-chip
>   flash

This should be fine as long as your VDD delay is long enough.  One thing
that is not well documented by Phillips -yet- is the current consumption on
the LPC214x series running at different clock and peripheral speeds.

Joel

> This is a demo posted by Phillips apps that you might be 
> interested in:
> http://groups.yahoo.com/group/lpc2000/files/EE_demo.zip 

Demo is basically sound but has a few glaring bugs that mean the code in
the zip won't actually work properly !
I'll send an update to phillips_apps today (a working version), but
unfortunately it has also been modified to suit my application, so a bit
of a merge will be necessary rather than a replacement.

Cheers,
Bruce

gen_4p

>> > - during operation update user data in RAM only
>>
>> I'd store the RAM copy from time to time in the back-ground
>>
>
> Unfortunately this is not going to work for me (so i'd love to...).
> The system in design is a sound development system with 10 ms cycle,
> and max I can miss is one cycle once in a while. So there is no way I
> can spend 400ms for sector erasing and backing data up.

Isn't sector erasing self-timed ? Maybe you need to do it manualy, not via
IAP ?

>> > - on power-down use VDD delay to store RAM user data array in on-
>> >   chip flash
>
> Also I would like to make sure again. According to the ee_demo,
> though code is executed from the main flash, all operations on a
> flash writing are done through the bootloader/IAP. Is it right?
>
> And I do have my doubts on implementing data storage in on-chip flash
> (from development efforts point of view). SPI external flash for $1
> will do the same and, probably, with a lot less efforts.

External flash or EEPROM has IMHO a lot of advantages though the 
disadvantage
of having one chip more.

Pros:
- up to 1 million times erasable (FRAM even more, but more expensive)
- erasing will not disturb the LPCs program flow. IAP means IIRC the 
interrupts are locked because you can not run from flash while erasing.
- there are EEPROM with a large buffer, so writing is only the SPI speed.


-- 
42Bastian Schick