Lpc2000

> FIFO.  When you get an interrupt you can sit in a loop and stuff the FIFO
> full before returning.  That nicely lowers the interrupt overhead by a
> factor of 15 or 16.  On the down side the main service body will take
> longer, maybe not a full 15x longer but longer so that each individual
> interrupt may be longer and increase your latency.  If you just put in one
> character and exit the interrupt it will probably act just as you say.

How do you then know when the FIFO is full ? There is nothing
accessible to tell you.
Do you maintain a counter loop that lets you only write up to 16 chars
in the FIFO ?
The description on page 89 is really ambiguous, it implies that if 2 or more
chars are in the FIFO _and_ the shiftregister has just flushed out a char,
that THRE will set too.
THRE when FIFO empty "provided" certain init conditions have been met.
Is this referring to the char delay so no INTs will issue straight away at
start up ?
I guess so.

-- Kris