At 06:38 AM 2/19/04 +1100, you wrote:
> > FIFO. When you get an interrupt you can sit in a loop and stuff the FIFO
> > full before returning. That nicely lowers the interrupt overhead by a
> > factor of 15 or 16. On the down side the main service body will take
> > longer, maybe not a full 15x longer but longer so that each individual
> > interrupt may be longer and increase your latency. If you just put in one
> > character and exit the interrupt it will probably act just as you say.
>
>How do you then know when the FIFO is full ? There is nothing
>accessible to tell you.
>Do you maintain a counter loop that lets you only write up to 16 chars
>in the FIFO ?
>The description on page 89 is really ambiguous, it implies that if 2 or more
>chars are in the FIFO _and_ the shiftregister has just flushed out a char,
>that THRE will set too.
>THRE when FIFO empty "provided" certain init conditions have been met.
>Is this referring to the char delay so no INTs will issue straight away at
>start up ?
>I guess so.
I don't see another way than maintaining a counter. From National's data
sheet pg 19
When the XMIT FIFO and transmitter interrupts are enabled
(FCR0e1, IER1e1), XMIT interrupts will occur as follows:
A. The transmitter holding register interrupt (02) occurs
when the XMIT FIFO is empty; it is cleared as soon as
the transmitter holding register is written to (1 to 16 characters
may be written to the XMIT FIFO while servicing
this interrupt) or the IIR is read.
B. The transmitter FIFO empty indications will be delayed 1
character time minus the last stop bit time whenever the
following occurs: THREe1 and there have not been at
least two bytes at the same time in the transmit FIFO,
since the last THREe1. The first transmitter interrupt after
changing FCR0 will be immediate, if it is enabled.
Character timeout and RCVR FIFO trigger level interrupts
have the same priority as the current received data available
interrupt; XMIT FIFO empty has the same priority as
the current transmitter holding register empty interrupt.
It's a little easier to follow in the datasheet.
" 'Freedom' has no meaning of itself. There are always restrictions,
be they legal, genetic, or physical. If you don't believe me, try to
chew a radio signal. "
Kelvin Throop, IIIMessage
Re: [lpc2000] UART TX FIFO and INTs problem
2004-02-18 by Robert Adsett
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