Lpc2000

andersryl wrote:

>Thanks for your reply.
>
>The fact that the ISR's servicing the interrupts from both UART1 and 
>Timer0 work up to a certain point makes me think that the ISR's are 
>working properly. I'm not 100% sure though...
>
>Here is the code for the ISR's if anyone wants to have a look:
>main.c:
>*******************************
>void UART1Handler (void) {
>   BYTE stat;
>   WORD i;
>   stat = U1IIR & 0x0F;
>
>   while (stat != 1) {
>      switch (stat) {
>      case 4:	/* Rx FIFO filled to threshold level. Read bytes */
>         for (i=0; i<RX_FIFO_THRESHOLD; i++) {
>            uart0RxBuffer[uart0RxByteCounter++ % uart0RxBufferSize] 
>= U1RBR;
>         }
>         break;
>      case 12:	/* Old bytes still in RX FIFO. Read the bytes */
>         while ((U1LSR & 0x01) == 1) {
>            uart0RxBuffer[uart0RxByteCounter++ % uart0RxBufferSize] 
>= U1RBR;
>         }
>         break;
>      default:		/* Unidentified interrupt cause */
>         sendString("Error:");   /* Debug print-out */
>         sendString(stat);       /* Debug print-out */
>         break;
>      }
>
>      stat = U1IIR & 0x0F;
>   }
>
>   VICVectAddr = 0;	// Enable new IRQ-interrupts
>
>   return;
>}
>  
>
FWIW, I'd declare stat as volatile:

volatile BYTE stat;

Just to ensure it isn't going to get optimized into a static (assumed 
unchanging) value.

TomW


-- 
Tom Walsh - WN3L - Embedded Systems Consultant
http://openhardware.net, http://cyberiansoftware.com
"Windows? No thanks, I have work to do..."
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