Lpc2000

Hi guys,

The uCOS-II RTOS port for the ARM processor defines an
OS_ENTER_CRITICAL and OS_EXIT_CRITICAL pair of macros,
inside which you can perform atomic (well, non-interruptible
operations). These aren't just limited to the RTOS
though.

The code snippet below is based on:

http://www.atmel.com/dyn/resources/prod_documents/DOC1156.PDF

Perhaps you want to add something like this to
protect your watchdog code.

Dave



from the UCOS-II os_cpu.h header:

#define  OS_ENTER_CRITICAL()  {cpu_sr = OS_CPU_SR_Save();}
#define  OS_EXIT_CRITICAL()   {OS_CPU_SR_Restore(cpu_sr);}

from the UCOS-II os_cpu_a.asm code:

@*********************************************************************************************************
@                                   CRITICAL SECTION METHOD 3 FUNCTION
@
@ Description: Disable/Enable interrupts by preserving the state of 
interrupts.  Generally speaking you
@              would store the state of the interrupt disable flag in 
the local variable 'cpu_sr' and then
@              disable interrupts.  'cpu_sr' is allocated in all of 
uC/OS-II's functions that need to
@              disable interrupts.  You would restore the interrupt 
disable state by copying back 'cpu_sr'
@              into the CPU's status register.
@
@ Prototypes :     OS_CPU_SR  OS_CPU_SR_Save(void);
@                  void       OS_CPU_SR_Restore(OS_CPU_SR cpu_sr);
@
@
@ Note(s)    : 1) These functions are used in general like this:
@
@                 void Task (void *p_arg)
@                 {
@                 #if OS_CRITICAL_METHOD == 3          /* Allocate 
storage for CPU status register */
@                     OS_CPU_SR  cpu_sr;
@                 #endif
@
@                          :
@                          :
@                     OS_ENTER_CRITICAL();             /* cpu_sr = 
OS_CPU_SaveSR();                */
@                          :
@                          :
@                     OS_EXIT_CRITICAL();              /* 
OS_CPU_RestoreSR(cpu_sr);                */
@                          :
@                          :
@                 }
@
@              2) OS_CPU_SR_Save() is implemented as recommended by 
Atmel's application note:
@
@                    "Disabling Interrupts at Processor Level"
@
@                 p328 of the ARM System Developers Guide has the first 
three asm statements and
@                 does not use the check.
@
@                 NOTE: the flags can ONLY be modified by a priviledged 
mode, so if you accidentally
@                 call this function from user-mode, the processor will 
lock up (in the loop check).
@
@*********************************************************************************************************

         .text
         .arm
	.align	2
	.func	OS_CPU_SR_Save

OS_CPU_SR_Save:
         MRS     R0,CPSR                     @ Set IRQ and FIQ bits in 
CPSR to disable all interrupts
         ORR     R1,R0,#I_Bit|F_Bit
         MSR     CPSR_c,R1

         @ Interrupt disable check:
         @
         @ This is a slight variation on the Atmel app note code,
         @ as it checks that both FIQ and IRQ disable bits get set.

         MRS     R1,CPSR                     @ Confirm that CPSR 
contains the proper interrupt disable flags
         AND     R1,R1,#I_Bit|F_Bit
         CMP     R1,#I_Bit|F_Bit
         BNE     OS_CPU_SR_Save              @ Not properly disabled 
(try again)

         MOV     PC,LR                       @ Disabled, return the 
original CPSR contents in R0
	.endfunc

         .text
         .arm
	.align	2
	.func	OS_CPU_SR_Restore

OS_CPU_SR_Restore:
         MSR     CPSR_c,R0
         MOV     PC,LR
	.endfunc