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Problem with watchdog

Problem with watchdog

2005-12-06 by Ake Hedman, eurosource

Hi all.

I am trying to enable the watchdog but the result is a total hang of the 
board. Not even the bootloader is possible to reach after the crash and 
I have to reapply power with P0.14 low to get access to the botloader 
again. Reset is not enough.

The code to initialize the watchdog is

    // initialize the watchdog timer
    WDTC = 0xffffffff; // 15000000;                        // One second 
= 15000000
    WDMOD = WDEN | WDRESET;                    // Activate watchdog
    WDFEED = 0xAA; WDFEED = 0x55;

I must have misunderstood the WD functionality. What am I doing wrong? 
In the above code the watchdog should not trigger until 5 minutes 
elapsed so even if a vector should be wrong the code that follow should 
run for a while but as soon as I write to the WDMOD register I get a hang.

/Ake

-- 
 ---
Ake Hedman (YAP - Yet Another Programmer)
eurosource, Brattbergavägen 17, 820 50 LOS, Sweden
Phone: (46) 657 413430 Cellular: (46) 73 84 84 102
Company home: http://www.eurosource.se      
Kryddor/Te/Kaffe: http://www.brattberg.com
Personal homepage: http://www.eurosource.se/akhe
Automated home: http://www.vscp.org

Re: [lpc2000] Problem with watchdog

2005-12-06 by Jim Parziale

Assuming you have the correct definitions for your symbols, the only thing I
can think of is setting the timeout to the largest integer like that.  Maybe
you could try a different large integer?

These are what you should be using:
WDEN = BIT(0) = 0x00000001
WDRESET = BIT(1) = 0x00000002
WDMOD  = (uint8_t *)(0xE0000000)
WDTC      = (uint32_t *)(0xE0000004)
WDFEED = (uint8_t *)(0xE0000008)

----------------------------------------------------------
Jim Parziale
Email: nuncio.bitis@...
Malden, MA
----------------------------------------------------------

On 12/6/05, Ake Hedman, eurosource <akhe@...> wrote:
>
>  Hi all.
>
> I am trying to enable the watchdog but the result is a total hang of the
> board. Not even the bootloader is possible to reach after the crash and
> I have to reapply power with P0.14 low to get access to the botloader
> again. Reset is not enough.
>
> The code to initialize the watchdog is
>
>     // initialize the watchdog timer
>     WDTC = 0xffffffff; // 15000000;                        // One second
> = 15000000
>     WDMOD = WDEN | WDRESET;                    // Activate watchdog
>     WDFEED = 0xAA; WDFEED = 0x55;
>
> I must have misunderstood the WD functionality. What am I doing wrong?
> In the above code the watchdog should not trigger until 5 minutes
> elapsed so even if a vector should be wrong the code that follow should
> run for a while but as soon as I write to the WDMOD register I get a hang.
>
> /Ake
>
> --
> ---
> Ake Hedman (YAP - Yet Another Programmer)
> eurosource, Brattbergavägen 17, 820 50 LOS, Sweden
> Phone: (46) 657 413430 Cellular: (46) 73 84 84 102
> Company home: http://www.eurosource.se
> Kryddor/Te/Kaffe: http://www.brattberg.com
> Personal homepage: http://www.eurosource.se/akhe
> Automated home: http://www.vscp.org
>
>


[Non-text portions of this message have been removed]

Re: [lpc2000] Problem with watchdog

2005-12-06 by Ake Hedman, eurosource

Jim Parziale wrote:

> Assuming you have the correct definitions for your symbols, the only 
> thing I
> can think of is setting the timeout to the largest integer like that.  
> Maybe
> you could try a different large integer?
>
> These are what you should be using:
> WDEN = BIT(0) = 0x00000001
> WDRESET = BIT(1) = 0x00000002
> WDMOD  = (uint8_t *)(0xE0000000)
> WDTC      = (uint32_t *)(0xE0000004)
> WDFEED = (uint8_t *)(0xE0000008)

Jim,

yes my defines are the same and yes I have tested with other values for 
the watchdog period. According to the manual the watchdog timer should 
start when the 0xaa, 0x55 sequence is written but my problems are occurs 
as soon as I write to the WDMOD register.

What situations can prevent the bootloader from working after a reset?

/Ake

>
> ----------------------------------------------------------
> Jim Parziale
> Email: nuncio.bitis@gmail.com
> Malden, MA
> ----------------------------------------------------------
>
> On 12/6/05, Ake Hedman, eurosource <akhe@...> wrote:
> >
> >  Hi all.
> >
> > I am trying to enable the watchdog but the result is a total hang of the
> > board. Not even the bootloader is possible to reach after the crash and
> > I have to reapply power with P0.14 low to get access to the botloader
> > again. Reset is not enough.
> >
> > The code to initialize the watchdog is
> >
> >     // initialize the watchdog timer
> >     WDTC = 0xffffffff; // 15000000;                        // One second
> > = 15000000
> >     WDMOD = WDEN | WDRESET;                    // Activate watchdog
> >     WDFEED = 0xAA; WDFEED = 0x55;
> >
> > I must have misunderstood the WD functionality. What am I doing wrong?
> > In the above code the watchdog should not trigger until 5 minutes
> > elapsed so even if a vector should be wrong the code that follow should
> > run for a while but as soon as I write to the WDMOD register I get a 
> hang.
> >
> > /Ake
> >
> > --
> > ---
> > Ake Hedman (YAP - Yet Another Programmer)
> > eurosource, Brattbergavägen 17, 820 50 LOS, Sweden
> > Phone: (46) 657 413430 Cellular: (46) 73 84 84 102
> > Company home: http://www.eurosource.se
> > Kryddor/Te/Kaffe: http://www.brattberg.com
> > Personal homepage: http://www.eurosource.se/akhe
> > Automated home: http://www.vscp.org
> >
> >
>
>
> [Non-text portions of this message have been removed]
>
>
> ------------------------------------------------------------------------
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>
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>       <http://groups.yahoo.com/group/lpc2000>" on the web.
>        
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>
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> ------------------------------------------------------------------------
>


-- 
 ---
Ake Hedman (YAP - Yet Another Programmer)
eurosource, Brattbergavägen 17, 820 50 LOS, Sweden
Phone: (46) 657 413430 Cellular: (46) 73 84 84 102
Company home: http://www.eurosource.se      
Kryddor/Te/Kaffe: http://www.brattberg.com
Personal homepage: http://www.eurosource.se/akhe
Automated home: http://www.vscp.org



[Non-text portions of this message have been removed]

Re: [lpc2000] Problem with watchdog

2005-12-06 by Ake Hedman, eurosource

I have found part of this problem. The GNU compiler translates

WDFEED = 0xAA; WDFEED = 0x55;

to

710 04c4 8E22A0E3         mov    r2, #-536870904
711 04c8 5530E0E3         mvn    r3, #85
712 04cc 0030C2E5         strb    r3, [r2, #0]
713 04d0 8E22A0E3         mov    r2, #-536870904
714 04d4 5530A0E3         mov    r3, #85
715 04d8 0030C2E5         strb    r3, [r2, #0]


i.e. just writing 0x55.    This is done even if compiled with 
optimization of.

Anyone know how to work around this?

Watchdog registers are currently defined as

// Watchdog
#define WDMOD          (*((volatile unsigned char *) 0xE0000000))
#define WDTC           (*((volatile unsigned long *) 0xE0000004))
#define WDFEED         (*((volatile unsigned char *) 0xE0000008))
#define WDTV           (*((volatile unsigned long *) 0xE000000C))



/Ake


Ake Hedman, eurosource wrote:

>
> Jim Parziale wrote:
>
> > Assuming you have the correct definitions for your symbols, the only
> > thing I
> > can think of is setting the timeout to the largest integer like that. 
> > Maybe
> > you could try a different large integer?
> >
> > These are what you should be using:
> > WDEN = BIT(0) = 0x00000001
> > WDRESET = BIT(1) = 0x00000002
> > WDMOD  = (uint8_t *)(0xE0000000)
> > WDTC      = (uint32_t *)(0xE0000004)
> > WDFEED = (uint8_t *)(0xE0000008)
>
> Jim,
>
> yes my defines are the same and yes I have tested with other values for
> the watchdog period. According to the manual the watchdog timer should
> start when the 0xaa, 0x55 sequence is written but my problems are occurs
> as soon as I write to the WDMOD register.
>
> What situations can prevent the bootloader from working after a reset?
>
> /Ake
>
> >
> > ----------------------------------------------------------
> > Jim Parziale
> > Email: nuncio.bitis@...
> > Malden, MA
> > ----------------------------------------------------------
> >
> > On 12/6/05, Ake Hedman, eurosource <akhe@brattberg.com> wrote:
> > >
> > >  Hi all.
> > >
> > > I am trying to enable the watchdog but the result is a total hang 
> of the
> > > board. Not even the bootloader is possible to reach after the 
> crash and
> > > I have to reapply power with P0.14 low to get access to the botloader
> > > again. Reset is not enough.
> > >
> > > The code to initialize the watchdog is
> > >
> > >     // initialize the watchdog timer
> > >     WDTC = 0xffffffff; // 15000000;                        // One 
> second
> > > = 15000000
> > >     WDMOD = WDEN | WDRESET;                    // Activate watchdog
> > >     WDFEED = 0xAA; WDFEED = 0x55;
> > >
> > > I must have misunderstood the WD functionality. What am I doing wrong?
> > > In the above code the watchdog should not trigger until 5 minutes
> > > elapsed so even if a vector should be wrong the code that follow 
> should
> > > run for a while but as soon as I write to the WDMOD register I get a
> > hang.
> > >
> > > /Ake
> > >
> > > --
> > > ---
> > > Ake Hedman (YAP - Yet Another Programmer)
> > > eurosource, Brattbergavägen 17, 820 50 LOS, Sweden
> > > Phone: (46) 657 413430 Cellular: (46) 73 84 84 102
> > > Company home: http://www.eurosource.se
> > > Kryddor/Te/Kaffe: http://www.brattberg.com
> > > Personal homepage: http://www.eurosource.se/akhe
> > > Automated home: http://www.vscp.org
> > >
> > >
> >
> >
> > [Non-text portions of this message have been removed]
> >
> >
> > ------------------------------------------------------------------------
> > YAHOO! GROUPS LINKS
> >
> >     *  Visit your group "lpc2000
> >       <http://groups.yahoo.com/group/lpc2000>" on the web.
> >       
> >     *  To unsubscribe from this group, send an email to:
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> >       Service <http://docs.yahoo.com/info/terms/>.
> >
> >
> > ------------------------------------------------------------------------
> >
>
>
> -- 
> ---
> Ake Hedman (YAP - Yet Another Programmer)
> eurosource, Brattbergavägen 17, 820 50 LOS, Sweden
> Phone: (46) 657 413430 Cellular: (46) 73 84 84 102
> Company home: http://www.eurosource.se     
> Kryddor/Te/Kaffe: http://www.brattberg.com
> Personal homepage: http://www.eurosource.se/akhe
> Automated home: http://www.vscp.org
>
>
>
> [Non-text portions of this message have been removed]
>
>
>
> SPONSORED LINKS
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> <http://groups.yahoo.com/gads?t=ms&k=Microprocessor&w1=Microprocessor&w2=Microcontrollers&w3=Pic+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=tsVC-J9hJ5qyXg0WPR0l6g> 
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>
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> <http://groups.yahoo.com/gads?t=ms&k=8051+microprocessor&w1=Microprocessor&w2=Microcontrollers&w3=Pic+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=1Ipf1Fjfbd_HVIlekkDP-A> 
>
>
>
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-- 
 ---
Ake Hedman (YAP - Yet Another Programmer)
eurosource, Brattbergavägen 17, 820 50 LOS, Sweden
Phone: (46) 657 413430 Cellular: (46) 73 84 84 102
Company home: http://www.eurosource.se      
Kryddor/Te/Kaffe: http://www.brattberg.com
Personal homepage: http://www.eurosource.se/akhe
Automated home: http://www.vscp.org



[Non-text portions of this message have been removed]

Re: [lpc2000] Problem with watchdog

2005-12-06 by Bill Knight

Actually it is writing 0xAA then 0x55.  The second line of the
disassembly is mvn (move negative).  It loads the inverted value
of 85=0x55 (0xFFFFFFAA) into r3.  The next line stores the low
order byte WFEED (-536870904=0xE0000008).

Regards
-Bill Knight
R O SoftWare &
http://www.theARMPatch.com
Show quoted textHide quoted text
On Tue, 06 Dec 2005 21:22:21 +0100, Ake Hedman, eurosource wrote:

>I have found part of this problem. The GNU compiler translates

>WDFEED = 0xAA; WDFEED = 0x55;

>to

>710 04c4 8E22A0E3         mov    r2, #-536870904
>711 04c8 5530E0E3         mvn    r3, #85
>712 04cc 0030C2E5         strb    r3, [r2, #0]
>713 04d0 8E22A0E3         mov    r2, #-536870904
>714 04d4 5530A0E3         mov    r3, #85
>715 04d8 0030C2E5         strb    r3, [r2, #0]


>i.e. just writing 0x55.    This is done even if compiled with 
>optimization of.

>Anyone know how to work around this?

>Watchdog registers are currently defined as

>// Watchdog
>#define WDMOD          (*((volatile unsigned char *) 0xE0000000))
>#define WDTC           (*((volatile unsigned long *) 0xE0000004))
>#define WDFEED         (*((volatile unsigned char *) 0xE0000008))
>#define WDTV           (*((volatile unsigned long *) 0xE000000C))



>/Ake


>Ake Hedman, eurosource wrote:

>>
>> Jim Parziale wrote:
>>
>> > Assuming you have the correct definitions for your symbols, the only
>> > thing I
>> > can think of is setting the timeout to the largest integer like that. 
>> > Maybe
>> > you could try a different large integer?
>> >
>> > These are what you should be using:
>> > WDEN = BIT(0) = 0x00000001
>> > WDRESET = BIT(1) = 0x00000002
>> > WDMOD  = (uint8_t *)(0xE0000000)
>> > WDTC      = (uint32_t *)(0xE0000004)
>> > WDFEED = (uint8_t *)(0xE0000008)
>>
>> Jim,
>>
>> yes my defines are the same and yes I have tested with other values for
>> the watchdog period. According to the manual the watchdog timer should
>> start when the 0xaa, 0x55 sequence is written but my problems are occurs
>> as soon as I write to the WDMOD register.
>>
>> What situations can prevent the bootloader from working after a reset?
>>
>> /Ake
>>
>> >
>> > ----------------------------------------------------------
>> > Jim Parziale
>> > Email: nuncio.bitis@...
>> > Malden, MA
>> > ----------------------------------------------------------
>> >
>> > On 12/6/05, Ake Hedman, eurosource <akhe@...> wrote:
>> > >
>> > >  Hi all.
>> > >
>> > > I am trying to enable the watchdog but the result is a total hang 
>> of the
>> > > board. Not even the bootloader is possible to reach after the 
>> crash and
>> > > I have to reapply power with P0.14 low to get access to the botloader
>> > > again. Reset is not enough.
>> > >
>> > > The code to initialize the watchdog is
>> > >
>> > >     // initialize the watchdog timer
>> > >     WDTC = 0xffffffff; // 15000000;                        // One 
>> second
>> > > = 15000000
>> > >     WDMOD = WDEN | WDRESET;                    // Activate watchdog
>> > >     WDFEED = 0xAA; WDFEED = 0x55;
>> > >
>> > > I must have misunderstood the WD functionality. What am I doing wrong?
>> > > In the above code the watchdog should not trigger until 5 minutes
>> > > elapsed so even if a vector should be wrong the code that follow 
>> should
>> > > run for a while but as soon as I write to the WDMOD register I get a
>> > hang.
>> > >
>> > > /Ake
>> > >
>> > > --
>> > > ---
>> > > Ake Hedman (YAP - Yet Another Programmer)
>> > > eurosource, Brattbergavägen 17, 820 50 LOS, Sweden
>> > > Phone: (46) 657 413430 Cellular: (46) 73 84 84 102
>> > > Company home: http://www.eurosource.se
>> > > Kryddor/Te/Kaffe: http://www.brattberg.com
>> > > Personal homepage: http://www.eurosource.se/akhe
>> > > Automated home: http://www.vscp.org
>> > >
>> > >
>> >
>> >
>> > [Non-text portions of this message have been removed]
>> >
>> >
>> > ------------------------------------------------------------------------
>> > YAHOO! GROUPS LINKS
>> >
>> >     *  Visit your group "lpc2000
>> >       <http://groups.yahoo.com/group/lpc2000>" on the web.
>> >       
>> >     *  To unsubscribe from this group, send an email to:
>> >        lpc2000-unsubscribe@yahoogroups.com
>> >       <mailto:lpc2000-unsubscribe@yahoogroups.com?subject=Unsubscribe>
>> >       
>> >     *  Your use of Yahoo! Groups is subject to the Yahoo! Terms of
>> >       Service <http://docs.yahoo.com/info/terms/>.
>> >
>> >
>> > ------------------------------------------------------------------------
>> >
>>
>>
>> -- 
>> ---
>> Ake Hedman (YAP - Yet Another Programmer)
>> eurosource, Brattbergavägen 17, 820 50 LOS, Sweden
>> Phone: (46) 657 413430 Cellular: (46) 73 84 84 102
>> Company home: http://www.eurosource.se     
>> Kryddor/Te/Kaffe: http://www.brattberg.com
>> Personal homepage: http://www.eurosource.se/akhe
>> Automated home: http://www.vscp.org
>>
>>
>>
>> [Non-text portions of this message have been removed]
>>
>>
>>
>> SPONSORED LINKS
>> Microprocessor 
>> <http://groups.yahoo.com/gads?t=ms&k=Microprocessor&w1=Microprocessor&w2=Microcontrollers&w3=Pic+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=tsVC-J9hJ5qyXg0WPR0l6g> 
>> 	Microcontrollers 
>> <http://groups.yahoo.com/gads?t=ms&k=Microcontrollers&w1=Microprocessor&w2=Microcontrollers&w3=Pic+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=DvJVNqC_pqRTm8Xq01nxwg> 
>> 	Pic microcontrollers 
>> <http://groups.yahoo.com/gads?t=ms&k=Pic+microcontrollers&w1=Microprocessor&w2=Microcontrollers&w3=Pic+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=TpkoX4KofDJ7c6LyBvUqVQ> 
>>
>> 8051 microprocessor 
>> <http://groups.yahoo.com/gads?t=ms&k=8051+microprocessor&w1=Microprocessor&w2=Microcontrollers&w3=Pic+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=1Ipf1Fjfbd_HVIlekkDP-A> 
>>
>>
>>
>> ------------------------------------------------------------------------
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>>     *  Visit your group "lpc2000
>>       <http://groups.yahoo.com/group/lpc2000>" on the web.
>>        
>>     *  To unsubscribe from this group, send an email to:
>>        lpc2000-unsubscribe@yahoogroups.com
>>       <mailto:lpc2000-unsubscribe@yahoogroups.com?subject=Unsubscribe>
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>>       Service <http://docs.yahoo.com/info/terms/>.
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>> ------------------------------------------------------------------------
>>


>-- 
> ---
>Ake Hedman (YAP - Yet Another Programmer)
>eurosource, Brattbergavägen 17, 820 50 LOS, Sweden
>Phone: (46) 657 413430 Cellular: (46) 73 84 84 102
>Company home: http://www.eurosource.se      
>Kryddor/Te/Kaffe: http://www.brattberg.com
>Personal homepage: http://www.eurosource.se/akhe
>Automated home: http://www.vscp.org



>[Non-text portions of this message have been removed]




> 
>Yahoo! Groups Links



>

Re: [lpc2000] Problem with watchdog

2005-12-06 by Tom Walsh

Ake Hedman, eurosource wrote:

>I have found part of this problem. The GNU compiler translates
>
>WDFEED = 0xAA; WDFEED = 0x55;
>
>to
>
>710 04c4 8E22A0E3         mov    r2, #-536870904
>711 04c8 5530E0E3         mvn    r3, #85
>712 04cc 0030C2E5         strb    r3, [r2, #0]
>713 04d0 8E22A0E3         mov    r2, #-536870904
>714 04d4 5530A0E3         mov    r3, #85
>715 04d8 0030C2E5         strb    r3, [r2, #0]
>
>
>i.e. just writing 0x55.    This is done even if compiled with 
>optimization of.
>
>Anyone know how to work around this?
>
>  
>
do you have WDFEED declared as "volatile"?  This tells gcc not to 
optimize out accesses to that memory, that the memory location may 
change between readings (as in the case of an interrupt writing to that 
location).

example:

volatile char * WDFEED;





>Watchdog registers are currently defined as
>
>// Watchdog
>#define WDMOD          (*((volatile unsigned char *) 0xE0000000))
>#define WDTC           (*((volatile unsigned long *) 0xE0000004))
>#define WDFEED         (*((volatile unsigned char *) 0xE0000008))
>#define WDTV           (*((volatile unsigned long *) 0xE000000C))
>
>
>
>/Ake
>
>
>Ake Hedman, eurosource wrote:
>
>  
>
>>Jim Parziale wrote:
>>
>>    
>>
>>>Assuming you have the correct definitions for your symbols, the only
>>>thing I
>>>can think of is setting the timeout to the largest integer like that. 
>>>Maybe
>>>you could try a different large integer?
>>>
>>>These are what you should be using:
>>>WDEN = BIT(0) = 0x00000001
>>>WDRESET = BIT(1) = 0x00000002
>>>WDMOD  = (uint8_t *)(0xE0000000)
>>>WDTC      = (uint32_t *)(0xE0000004)
>>>WDFEED = (uint8_t *)(0xE0000008)
>>>      
>>>
>>Jim,
>>
>>yes my defines are the same and yes I have tested with other values for
>>the watchdog period. According to the manual the watchdog timer should
>>start when the 0xaa, 0x55 sequence is written but my problems are occurs
>>as soon as I write to the WDMOD register.
>>
>>What situations can prevent the bootloader from working after a reset?
>>
>>/Ake
>>
>>    
>>
>>>----------------------------------------------------------
>>>Jim Parziale
>>>Email: nuncio.bitis@...
>>>Malden, MA
>>>----------------------------------------------------------
>>>
>>>On 12/6/05, Ake Hedman, eurosource <akhe@...> wrote:
>>>      
>>>
>>>> Hi all.
>>>>
>>>>I am trying to enable the watchdog but the result is a total hang 
>>>>        
>>>>
>>of the
>>    
>>
>>>>board. Not even the bootloader is possible to reach after the 
>>>>        
>>>>
>>crash and
>>    
>>
>>>>I have to reapply power with P0.14 low to get access to the botloader
>>>>again. Reset is not enough.
>>>>
>>>>The code to initialize the watchdog is
>>>>
>>>>    // initialize the watchdog timer
>>>>    WDTC = 0xffffffff; // 15000000;                        // One 
>>>>        
>>>>
>>second
>>    
>>
>>>>= 15000000
>>>>    WDMOD = WDEN | WDRESET;                    // Activate watchdog
>>>>    WDFEED = 0xAA; WDFEED = 0x55;
>>>>
>>>>I must have misunderstood the WD functionality. What am I doing wrong?
>>>>In the above code the watchdog should not trigger until 5 minutes
>>>>elapsed so even if a vector should be wrong the code that follow 
>>>>        
>>>>
>>should
>>    
>>
>>>>run for a while but as soon as I write to the WDMOD register I get a
>>>>        
>>>>
>>>hang.
>>>      
>>>
>>>>/Ake
>>>>
>>>>--
>>>>---
>>>>Ake Hedman (YAP - Yet Another Programmer)
>>>>eurosource, Brattbergav\ufffdgen 17, 820 50 LOS, Sweden
>>>>Phone: (46) 657 413430 Cellular: (46) 73 84 84 102
>>>>Company home: http://www.eurosource.se
>>>>Kryddor/Te/Kaffe: http://www.brattberg.com
>>>>Personal homepage: http://www.eurosource.se/akhe
>>>>Automated home: http://www.vscp.org
>>>>
>>>>
>>>>        
>>>>
>>>[Non-text portions of this message have been removed]
>>>
>>>
>>>------------------------------------------------------------------------
>>>YAHOO! GROUPS LINKS
>>>
>>>    *  Visit your group "lpc2000
>>>      <http://groups.yahoo.com/group/lpc2000>" on the web.
>>>      
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>>>------------------------------------------------------------------------
>>>
>>>      
>>>
>>-- 
>>---
>>Ake Hedman (YAP - Yet Another Programmer)
>>eurosource, Brattbergavägen 17, 820 50 LOS, Sweden
>>Phone: (46) 657 413430 Cellular: (46) 73 84 84 102
>>Company home: http://www.eurosource.se     
>>Kryddor/Te/Kaffe: http://www.brattberg.com
>>Personal homepage: http://www.eurosource.se/akhe
>>Automated home: http://www.vscp.org
>>
>>
>>
>>[Non-text portions of this message have been removed]
>>
>>
>>
>>SPONSORED LINKS
>>Microprocessor 
>><http://groups.yahoo.com/gads?t=ms&k=Microprocessor&w1=Microprocessor&w2=Microcontrollers&w3=Pic+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=tsVC-J9hJ5qyXg0WPR0l6g> 
>>	Microcontrollers 
>><http://groups.yahoo.com/gads?t=ms&k=Microcontrollers&w1=Microprocessor&w2=Microcontrollers&w3=Pic+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=DvJVNqC_pqRTm8Xq01nxwg> 
>>	Pic microcontrollers 
>><http://groups.yahoo.com/gads?t=ms&k=Pic+microcontrollers&w1=Microprocessor&w2=Microcontrollers&w3=Pic+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=TpkoX4KofDJ7c6LyBvUqVQ> 
>>
>>8051 microprocessor 
>><http://groups.yahoo.com/gads?t=ms&k=8051+microprocessor&w1=Microprocessor&w2=Microcontrollers&w3=Pic+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=1Ipf1Fjfbd_HVIlekkDP-A> 
>>
>>
>>
>>------------------------------------------------------------------------
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>>
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>>      <http://groups.yahoo.com/group/lpc2000>" on the web.
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-- 
Tom Walsh - WN3L - Embedded Systems Consultant
http://openhardware.net, http://cyberiansoftware.com
"Windows? No thanks, I have work to do..."
----------------------------------------------------

Re: [lpc2000] Problem with watchdog

2005-12-06 by Tom Walsh

Bill Knight wrote:

>Actually it is writing 0xAA then 0x55.  The second line of the
>disassembly is mvn (move negative).  It loads the inverted value
>of 85=0x55 (0xFFFFFFAA) into r3.  The next line stores the low
>order byte WFEED (-536870904=0xE0000008).
>
>  
>
Ah!  Didn't notice that, you are correct.  Reading ARM asm still makes 
my head hurt!

TomW


>Regards
>-Bill Knight
>R O SoftWare &
>http://www.theARMPatch.com
>
>
>On Tue, 06 Dec 2005 21:22:21 +0100, Ake Hedman, eurosource wrote:
>
>  
>
>>I have found part of this problem. The GNU compiler translates
>>    
>>
>
>  
>
>>WDFEED = 0xAA; WDFEED = 0x55;
>>    
>>
>
>  
>
>>to
>>    
>>
>
>  
>
>>710 04c4 8E22A0E3         mov    r2, #-536870904
>>711 04c8 5530E0E3         mvn    r3, #85
>>712 04cc 0030C2E5         strb    r3, [r2, #0]
>>713 04d0 8E22A0E3         mov    r2, #-536870904
>>714 04d4 5530A0E3         mov    r3, #85
>>715 04d8 0030C2E5         strb    r3, [r2, #0]
>>    
>>
>
>
>  
>
>>i.e. just writing 0x55.    This is done even if compiled with 
>>optimization of.
>>    
>>
>
>  
>
>>Anyone know how to work around this?
>>    
>>
>
>  
>
>>Watchdog registers are currently defined as
>>    
>>
>
>  
>
>>// Watchdog
>>#define WDMOD          (*((volatile unsigned char *) 0xE0000000))
>>#define WDTC           (*((volatile unsigned long *) 0xE0000004))
>>#define WDFEED         (*((volatile unsigned char *) 0xE0000008))
>>#define WDTV           (*((volatile unsigned long *) 0xE000000C))
>>    
>>
>
>
>
>  
>
>>/Ake
>>    
>>
>
>
>  
>
>>Ake Hedman, eurosource wrote:
>>    
>>
>
>  
>
>>>Jim Parziale wrote:
>>>
>>>      
>>>
>>>>Assuming you have the correct definitions for your symbols, the only
>>>>thing I
>>>>can think of is setting the timeout to the largest integer like that. 
>>>>Maybe
>>>>you could try a different large integer?
>>>>
>>>>These are what you should be using:
>>>>WDEN = BIT(0) = 0x00000001
>>>>WDRESET = BIT(1) = 0x00000002
>>>>WDMOD  = (uint8_t *)(0xE0000000)
>>>>WDTC      = (uint32_t *)(0xE0000004)
>>>>WDFEED = (uint8_t *)(0xE0000008)
>>>>        
>>>>
>>>Jim,
>>>
>>>yes my defines are the same and yes I have tested with other values for
>>>the watchdog period. According to the manual the watchdog timer should
>>>start when the 0xaa, 0x55 sequence is written but my problems are occurs
>>>as soon as I write to the WDMOD register.
>>>
>>>What situations can prevent the bootloader from working after a reset?
>>>
>>>/Ake
>>>
>>>      
>>>
>>>>----------------------------------------------------------
>>>>Jim Parziale
>>>>Email: nuncio.bitis@...
>>>>Malden, MA
>>>>----------------------------------------------------------
>>>>
>>>>On 12/6/05, Ake Hedman, eurosource <akhe@...> wrote:
>>>>        
>>>>
>>>>> Hi all.
>>>>>
>>>>>I am trying to enable the watchdog but the result is a total hang 
>>>>>          
>>>>>
>>>of the
>>>      
>>>
>>>>>board. Not even the bootloader is possible to reach after the 
>>>>>          
>>>>>
>>>crash and
>>>      
>>>
>>>>>I have to reapply power with P0.14 low to get access to the botloader
>>>>>again. Reset is not enough.
>>>>>
>>>>>The code to initialize the watchdog is
>>>>>
>>>>>    // initialize the watchdog timer
>>>>>    WDTC = 0xffffffff; // 15000000;                        // One 
>>>>>          
>>>>>
>>>second
>>>      
>>>
>>>>>= 15000000
>>>>>    WDMOD = WDEN | WDRESET;                    // Activate watchdog
>>>>>    WDFEED = 0xAA; WDFEED = 0x55;
>>>>>
>>>>>I must have misunderstood the WD functionality. What am I doing wrong?
>>>>>In the above code the watchdog should not trigger until 5 minutes
>>>>>elapsed so even if a vector should be wrong the code that follow 
>>>>>          
>>>>>
>>>should
>>>      
>>>
>>>>>run for a while but as soon as I write to the WDMOD register I get a
>>>>>          
>>>>>
>>>>hang.
>>>>        
>>>>
>>>>>/Ake
>>>>>
>>>>>--
>>>>>---
>>>>>Ake Hedman (YAP - Yet Another Programmer)
>>>>>eurosource, Brattbergav\ufffdgen 17, 820 50 LOS, Sweden
>>>>>Phone: (46) 657 413430 Cellular: (46) 73 84 84 102
>>>>>Company home: http://www.eurosource.se
>>>>>Kryddor/Te/Kaffe: http://www.brattberg.com
>>>>>Personal homepage: http://www.eurosource.se/akhe
>>>>>Automated home: http://www.vscp.org
>>>>>
>>>>>
>>>>>          
>>>>>
>>>>[Non-text portions of this message have been removed]
>>>>
>>>>
>>>>------------------------------------------------------------------------
>>>>YAHOO! GROUPS LINKS
>>>>
>>>>    *  Visit your group "lpc2000
>>>>      <http://groups.yahoo.com/group/lpc2000>" on the web.
>>>>      
>>>>    *  To unsubscribe from this group, send an email to:
>>>>       lpc2000-unsubscribe@yahoogroups.com
>>>>      <mailto:lpc2000-unsubscribe@yahoogroups.com?subject=Unsubscribe>
>>>>      
>>>>    *  Your use of Yahoo! Groups is subject to the Yahoo! Terms of
>>>>      Service <http://docs.yahoo.com/info/terms/>.
>>>>
>>>>
>>>>------------------------------------------------------------------------
>>>>
>>>>        
>>>>
>>>-- 
>>>---
>>>Ake Hedman (YAP - Yet Another Programmer)
>>>eurosource, Brattbergavägen 17, 820 50 LOS, Sweden
>>>Phone: (46) 657 413430 Cellular: (46) 73 84 84 102
>>>Company home: http://www.eurosource.se     
>>>Kryddor/Te/Kaffe: http://www.brattberg.com
>>>Personal homepage: http://www.eurosource.se/akhe
>>>Automated home: http://www.vscp.org
>>>
>>>
>>>
>>>[Non-text portions of this message have been removed]
>>>
>>>
>>>
>>>SPONSORED LINKS
>>>Microprocessor 
>>><http://groups.yahoo.com/gads?t=ms&k=Microprocessor&w1=Microprocessor&w2=Microcontrollers&w3=Pic+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=tsVC-J9hJ5qyXg0WPR0l6g> 
>>>	Microcontrollers 
>>><http://groups.yahoo.com/gads?t=ms&k=Microcontrollers&w1=Microprocessor&w2=Microcontrollers&w3=Pic+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=DvJVNqC_pqRTm8Xq01nxwg> 
>>>	Pic microcontrollers 
>>><http://groups.yahoo.com/gads?t=ms&k=Pic+microcontrollers&w1=Microprocessor&w2=Microcontrollers&w3=Pic+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=TpkoX4KofDJ7c6LyBvUqVQ> 
>>>
>>>8051 microprocessor 
>>><http://groups.yahoo.com/gads?t=ms&k=8051+microprocessor&w1=Microprocessor&w2=Microcontrollers&w3=Pic+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=1Ipf1Fjfbd_HVIlekkDP-A> 
>>>
>>>
>>>
>>>------------------------------------------------------------------------
>>>YAHOO! GROUPS LINKS
>>>
>>>    *  Visit your group "lpc2000
>>>      <http://groups.yahoo.com/group/lpc2000>" on the web.
>>>       
>>>    *  To unsubscribe from this group, send an email to:
>>>       lpc2000-unsubscribe@yahoogroups.com
>>>      <mailto:lpc2000-unsubscribe@yahoogroups.com?subject=Unsubscribe>
>>>       
>>>    *  Your use of Yahoo! Groups is subject to the Yahoo! Terms of
>>>      Service <http://docs.yahoo.com/info/terms/>.
>>>
>>>
>>>------------------------------------------------------------------------
>>>
>>>      
>>>
>
>
>  
>
>>-- 
>>---
>>Ake Hedman (YAP - Yet Another Programmer)
>>eurosource, Brattbergavägen 17, 820 50 LOS, Sweden
>>Phone: (46) 657 413430 Cellular: (46) 73 84 84 102
>>Company home: http://www.eurosource.se      
>>Kryddor/Te/Kaffe: http://www.brattberg.com
>>Personal homepage: http://www.eurosource.se/akhe
>>Automated home: http://www.vscp.org
>>    
>>
>
>
>
>  
>
>>[Non-text portions of this message have been removed]
>>    
>>
>
>
>
>
>  
>
>>Yahoo! Groups Links
>>    
>>
>
>
>
>  
>
>
>
>
>
>
>
>
>
> 
>Yahoo! Groups Links
>
>
>
> 
>
>
>  
>


-- 
Tom Walsh - WN3L - Embedded Systems Consultant
http://openhardware.net, http://cyberiansoftware.com
"Windows? No thanks, I have work to do..."
----------------------------------------------------

RE: [lpc2000] Problem with watchdog

2005-12-07 by Dan Beadle

Are  you "tickling" the watchdog?  Once enabled, you must reset the timer regularly - to tell the WDT that life is good.  Otherwise it will bite you by resetting (in a loop)

 

  _____  
Show quoted textHide quoted text
From: lpc2000@yahoogroups.com [mailto:lpc2000@yahoogroups.com] On Behalf Of Jim Parziale
Sent: Tuesday, December 06, 2005 7:37 AM
To: lpc2000@yahoogroups.com
Subject: Re: [lpc2000] Problem with watchdog

 

Assuming you have the correct definitions for your symbols, the only thing I
can think of is setting the timeout to the largest integer like that.  Maybe
you could try a different large integer?

These are what you should be using:
WDEN = BIT(0) = 0x00000001
WDRESET = BIT(1) = 0x00000002
WDMOD  = (uint8_t *)(0xE0000000)
WDTC      = (uint32_t *)(0xE0000004)
WDFEED = (uint8_t *)(0xE0000008)

----------------------------------------------------------
Jim Parziale
Email: nuncio.bitis@gmail.com
Malden, MA
----------------------------------------------------------

On 12/6/05, Ake Hedman, eurosource <akhe@...> wrote:
>
>  Hi all.
>
> I am trying to enable the watchdog but the result is a total hang of the
> board. Not even the bootloader is possible to reach after the crash and
> I have to reapply power with P0.14 low to get access to the botloader
> again. Reset is not enough.
>
> The code to initialize the watchdog is
>
>     // initialize the watchdog timer
>     WDTC = 0xffffffff; // 15000000;                        // One second
> = 15000000
>     WDMOD = WDEN | WDRESET;                    // Activate watchdog
>     WDFEED = 0xAA; WDFEED = 0x55;
>
> I must have misunderstood the WD functionality. What am I doing wrong?
> In the above code the watchdog should not trigger until 5 minutes
> elapsed so even if a vector should be wrong the code that follow should
> run for a while but as soon as I write to the WDMOD register I get a hang.
>
> /Ake
>
> --
> ---
> Ake Hedman (YAP - Yet Another Programmer)
> eurosource, Brattbergavägen 17, 820 50 LOS, Sweden
> Phone: (46) 657 413430 Cellular: (46) 73 84 84 102
> Company home: http://www.eurosource.se
> Kryddor/Te/Kaffe: http://www.brattberg.com
> Personal homepage: http://www.eurosource.se/akhe
> Automated home: http://www.vscp.org
>
>


[Non-text portions of this message have been removed]




  _____  

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  _____  



[Non-text portions of this message have been removed]

Re: [lpc2000] Problem with watchdog

2005-12-07 by Ake Hedman, eurosource

Ooops..! Thanks a lot. wishful thinking from my part I guess. ;-)

I'm back on square one then. hmmm...  I really need to solve this.

I have done a small program that initialize the watchdog as of my 
previous example and then just loop while "feeding the dog"  just after 
a debug output on the serial channel. But the result is the same. No 
output and I have to hold p0.14 low and re power the board to be able to 
bootload it.

/Ake


Bill Knight wrote:

> Actually it is writing 0xAA then 0x55.  The second line of the
> disassembly is mvn (move negative).  It loads the inverted value
> of 85=0x55 (0xFFFFFFAA) into r3.  The next line stores the low
> order byte WFEED (-536870904=0xE0000008).
>
> Regards
> -Bill Knight
> R O SoftWare &
> http://www.theARMPatch.com
>
>
> On Tue, 06 Dec 2005 21:22:21 +0100, Ake Hedman, eurosource wrote:
>
> >I have found part of this problem. The GNU compiler translates
>
> >WDFEED = 0xAA; WDFEED = 0x55;
>
> >to
>
> >710 04c4 8E22A0E3         mov    r2, #-536870904
> >711 04c8 5530E0E3         mvn    r3, #85
> >712 04cc 0030C2E5         strb    r3, [r2, #0]
> >713 04d0 8E22A0E3         mov    r2, #-536870904
> >714 04d4 5530A0E3         mov    r3, #85
> >715 04d8 0030C2E5         strb    r3, [r2, #0]
>
>
> >i.e. just writing 0x55.    This is done even if compiled with
> >optimization of.
>
> >Anyone know how to work around this?
>
> >Watchdog registers are currently defined as
>
> >// Watchdog
> >#define WDMOD          (*((volatile unsigned char *) 0xE0000000))
> >#define WDTC           (*((volatile unsigned long *) 0xE0000004))
> >#define WDFEED         (*((volatile unsigned char *) 0xE0000008))
> >#define WDTV           (*((volatile unsigned long *) 0xE000000C))
>
>
>
> >/Ake
>
>
> >Ake Hedman, eurosource wrote:
>
> >>
> >> Jim Parziale wrote:
> >>
> >> > Assuming you have the correct definitions for your symbols, the only
> >> > thing I
> >> > can think of is setting the timeout to the largest integer like 
> that.
> >> > Maybe
> >> > you could try a different large integer?
> >> >
> >> > These are what you should be using:
> >> > WDEN = BIT(0) = 0x00000001
> >> > WDRESET = BIT(1) = 0x00000002
> >> > WDMOD  = (uint8_t *)(0xE0000000)
> >> > WDTC      = (uint32_t *)(0xE0000004)
> >> > WDFEED = (uint8_t *)(0xE0000008)
> >>
> >> Jim,
> >>
> >> yes my defines are the same and yes I have tested with other values for
> >> the watchdog period. According to the manual the watchdog timer should
> >> start when the 0xaa, 0x55 sequence is written but my problems are 
> occurs
> >> as soon as I write to the WDMOD register.
> >>
> >> What situations can prevent the bootloader from working after a reset?
> >>
> >> /Ake
> >>
> >> >
> >> > ----------------------------------------------------------
> >> > Jim Parziale
> >> > Email: nuncio.bitis@...
> >> > Malden, MA
> >> > ----------------------------------------------------------
> >> >
> >> > On 12/6/05, Ake Hedman, eurosource <akhe@...> wrote:
> >> > >
> >> > >  Hi all.
> >> > >
> >> > > I am trying to enable the watchdog but the result is a total hang
> >> of the
> >> > > board. Not even the bootloader is possible to reach after the
> >> crash and
> >> > > I have to reapply power with P0.14 low to get access to the 
> botloader
> >> > > again. Reset is not enough.
> >> > >
> >> > > The code to initialize the watchdog is
> >> > >
> >> > >     // initialize the watchdog timer
> >> > >     WDTC = 0xffffffff; // 15000000;                        // One
> >> second
> >> > > = 15000000
> >> > >     WDMOD = WDEN | WDRESET;                    // Activate watchdog
> >> > >     WDFEED = 0xAA; WDFEED = 0x55;
> >> > >
> >> > > I must have misunderstood the WD functionality. What am I doing 
> wrong?
> >> > > In the above code the watchdog should not trigger until 5 minutes
> >> > > elapsed so even if a vector should be wrong the code that follow
> >> should
> >> > > run for a while but as soon as I write to the WDMOD register I 
> get a
> >> > hang.
> >> > >
> >> > > /Ake
> >> > >
> >> > > --
> >> > > ---
> >> > > Ake Hedman (YAP - Yet Another Programmer)
> >> > > eurosource, Brattbergavägen 17, 820 50 LOS, Sweden
> >> > > Phone: (46) 657 413430 Cellular: (46) 73 84 84 102
> >> > > Company home: http://www.eurosource.se
> >> > > Kryddor/Te/Kaffe: http://www.brattberg.com
> >> > > Personal homepage: http://www.eurosource.se/akhe
> >> > > Automated home: http://www.vscp.org
> >> > >
> >> > >
> >> >
> >> >
> >> > [Non-text portions of this message have been removed]
> >> >
> >> >
> >> > 
> ------------------------------------------------------------------------
> >> > YAHOO! GROUPS LINKS
> >> >
> >> >     *  Visit your group "lpc2000
> >> >       <http://groups.yahoo.com/group/lpc2000>" on the web.
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> ------------------------------------------------------------------------
> >> >
> >>
> >>
> >> --
> >> ---
> >> Ake Hedman (YAP - Yet Another Programmer)
> >> eurosource, Brattbergavägen 17, 820 50 LOS, Sweden
> >> Phone: (46) 657 413430 Cellular: (46) 73 84 84 102
> >> Company home: http://www.eurosource.se    
> >> Kryddor/Te/Kaffe: http://www.brattberg.com
> >> Personal homepage: http://www.eurosource.se/akhe
> >> Automated home: http://www.vscp.org
> >>
> >>
> >>
> >> [Non-text portions of this message have been removed]
> >>
> >>
> >>
> >> SPONSORED LINKS
> >> Microprocessor
> >> 
> <http://groups.yahoo.com/gads?t=ms&k=Microprocessor&w1=Microprocessor&w2=Microcontrollers&w3=Pic+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=tsVC-J9hJ5qyXg0WPR0l6g 
> <http://groups.yahoo.com/gads?t=ms&k=Microprocessor&w1=Microprocessor&w2=Microcontrollers&w3=Pic+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=tsVC-J9hJ5qyXg0WPR0l6g>> 
>
> >>       Microcontrollers
> >> 
> <http://groups.yahoo.com/gads?t=ms&k=Microcontrollers&w1=Microprocessor&w2=Microcontrollers&w3=Pic+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=DvJVNqC_pqRTm8Xq01nxwg 
> <http://groups.yahoo.com/gads?t=ms&k=Microcontrollers&w1=Microprocessor&w2=Microcontrollers&w3=Pic+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=DvJVNqC_pqRTm8Xq01nxwg>> 
>
> >>       Pic microcontrollers
> >> 
> <http://groups.yahoo.com/gads?t=ms&k=Pic+microcontrollers&w1=Microprocessor&w2=Microcontrollers&w3=Pic+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=TpkoX4KofDJ7c6LyBvUqVQ 
> <http://groups.yahoo.com/gads?t=ms&k=Pic+microcontrollers&w1=Microprocessor&w2=Microcontrollers&w3=Pic+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=TpkoX4KofDJ7c6LyBvUqVQ>> 
>
> >>
> >> 8051 microprocessor
> >> 
> <http://groups.yahoo.com/gads?t=ms&k=8051+microprocessor&w1=Microprocessor&w2=Microcontrollers&w3=Pic+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=1Ipf1Fjfbd_HVIlekkDP-A 
> <http://groups.yahoo.com/gads?t=ms&k=8051+microprocessor&w1=Microprocessor&w2=Microcontrollers&w3=Pic+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=1Ipf1Fjfbd_HVIlekkDP-A>> 
>
> >>
> >>
> >>
> >> 
> ------------------------------------------------------------------------
> >> YAHOO! GROUPS LINKS
> >>
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Re: [lpc2000] Problem with watchdog

2005-12-07 by Ake Hedman, eurosource

Tom Walsh wrote:

> Ake Hedman, eurosource wrote:
>
> >I have found part of this problem. The GNU compiler translates
> >
> >WDFEED = 0xAA; WDFEED = 0x55;
> >
> >to
> >
> >710 04c4 8E22A0E3         mov    r2, #-536870904
> >711 04c8 5530E0E3         mvn    r3, #85
> >712 04cc 0030C2E5         strb    r3, [r2, #0]
> >713 04d0 8E22A0E3         mov    r2, #-536870904
> >714 04d4 5530A0E3         mov    r3, #85
> >715 04d8 0030C2E5         strb    r3, [r2, #0]
> >
> >
> >i.e. just writing 0x55.    This is done even if compiled with
> >optimization of.
> >
> >Anyone know how to work around this?
> >
> > 
> >
> do you have WDFEED declared as "volatile"?  This tells gcc not to
> optimize out accesses to that memory, that the memory location may
> change between readings (as in the case of an interrupt writing to that
> location).
>
> example:
>
> volatile char * WDFEED;
>
Thanks Tom,

Yes its defined as

#define WDFEED         (*((volatile unsigned char *) 0xE0000008))

forgetting volatile have bite me so many times during the years. 

/Ake


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 ---
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Re: [lpc2000] Problem with watchdog

2005-12-07 by Ake Hedman, eurosource

Dan Beadle wrote:

> Are  you "tickling" the watchdog?  Once enabled, you must reset the 
> timer regularly - to tell the WDT that life is good.  Otherwise it 
> will bite you by resetting (in a loop)
>
Hej Dan,

yes I feed the dog. I have also just tried to write a loop where I do 
nothing else then feeding the watchdog but I'm still seem to have the 
problem. Initialized with the largest watchdog timeout value (about 5 
minutes) I should have no problem with this for the first time. But in 
my case nothing works after the initialization.

As no one seem not to have problems with this I must do something 
stupid. I must be missing something.

The program works perfect until I initialize the watchdog BTW. 

/Ake

-- 
 ---
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Re: [lpc2000] Problem with watchdog

2005-12-07 by Ake Hedman, eurosource

I am still trying to solve my problems with the watchdog.

I have now scaled away most stuff of my application and can see that the 
problem occurs when either of three interrupts occur (UART0/UART1/I2C0) 
in the system. Without the watchdog everything works fine but if I 
enable the watchdog everything crashes. I have tried to just enable and 
trig one of the interrupts in turn but the situation is the same.

I'm totally out of clues at the moment so any (also things that might be 
considered dumb) are very welcome.

Regards
/Ake

Ake Hedman, eurosource wrote:

> Dan Beadle wrote:
>
> > Are  you "tickling" the watchdog?  Once enabled, you must reset the
> > timer regularly - to tell the WDT that life is good.  Otherwise it
> > will bite you by resetting (in a loop)
> >
> Hej Dan,
>
> yes I feed the dog. I have also just tried to write a loop where I do
> nothing else then feeding the watchdog but I'm still seem to have the
> problem. Initialized with the largest watchdog timeout value (about 5
> minutes) I should have no problem with this for the first time. But in
> my case nothing works after the initialization.
>
> As no one seem not to have problems with this I must do something
> stupid. I must be missing something.
>
> The program works perfect until I initialize the watchdog BTW.
>
> /Ake
>
> -- 
> ---
> Ake Hedman (YAP - Yet Another Programmer)
> eurosource, Brattbergavägen 17, 820 50 LOS, Sweden
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Re: Problem with watchdog

2005-12-07 by alberto

Hi,
I have the same problems, when I try to insert WD function it doesn't 
work anything, the compiler expands code in the same manner as you 
explains. register are defined as volatile. But PLL_FEED doesn't work 
in the same mode?

Alberto

Re: [lpc2000] Re: Problem with watchdog

2005-12-07 by Ake Hedman, eurosource

What device are you using?
Have you tried just a loop where you feed the watchdog just after you 
enable it? This works for me as long as I don't have any interrupts 
enabled.

As it only happens when interrupts are enabled for me and therefore my 
working theory at the moment is that something is wrong happens in the 
interrupt routines after all. Have no clue why this should manifest 
itself when the watchdog is enabled. With the lack of responses on my 
cry for help on this issue from other list members no one else does 
either. ;-(   or? ;-)

/Ake


alberto wrote:

> Hi,
> I have the same problems, when I try to insert WD function it doesn't
> work anything, the compiler expands code in the same manner as you
> explains. register are defined as volatile. But PLL_FEED doesn't work
> in the same mode?
>
> Alberto
>
>
>
>
>
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-- 
 ---
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eurosource, Brattbergavägen 17, 820 50 LOS, Sweden
Phone: (46) 657 413430 Cellular: (46) 73 84 84 102
Company home: http://www.eurosource.se      
Kryddor/Te/Kaffe: http://www.brattberg.com
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[Non-text portions of this message have been removed]

Re: Problem with watchdog

2005-12-07 by dr_danish_ali

Ok Ake, here's my dumb suggestion:

Try enabling the watchdog, but just to interrupt not reset?
You'll need an interrupt handler / VIC channel to do it - can you spare one?
That ISR need just raise a flag for now.

Once the watchdog is fed and running happily, you might then be able to enable resets on 
it.

Hope this helps,
Danish

--- In lpc2000@yahoogroups.com, "Ake Hedman, eurosource" <akhe@b...> wrote:
Show quoted textHide quoted text
>
> I am still trying to solve my problems with the watchdog.
> 
> I have now scaled away most stuff of my application and can see that the 
> problem occurs when either of three interrupts occur (UART0/UART1/I2C0) 
> in the system. Without the watchdog everything works fine but if I 
> enable the watchdog everything crashes. I have tried to just enable and 
> trig one of the interrupts in turn but the situation is the same.
> 
> I'm totally out of clues at the moment so any (also things that might be 
> considered dumb) are very welcome.
> 
> Regards
> /Ake

Re: [lpc2000] Problem with watchdog

2005-12-07 by 3gpabko

Hi there,
there is a note in the UM about the feeding sequence
of the PLL which says that the writing of 0xAA and
then 0x55 must be two consecutive VPB cycles. No
interrupts between them. For the WDT the text is
different it says that after feeding 0xAA "...the next
operation in the Watchdog register space should be a
WRITE (0x55) to the WDFEED register otherwise the
Watchdog is triggered."

May be the dog doesn't like to be interrupted when
feeding.
  
Regards

--- "Ake Hedman, eurosource" <akhe@...>
wrote:

> Hi all.
> 
> I am trying to enable the watchdog but the result is
> a total hang of the 
> board. Not even the bootloader is possible to reach
> after the crash and 
> I have to reapply power with P0.14 low to get access
> to the botloader 
> again. Reset is not enough.
> 
> The code to initialize the watchdog is
> 
>     // initialize the watchdog timer
>     WDTC = 0xffffffff; // 15000000;                 
>       // One second 
> = 15000000
>     WDMOD = WDEN | WDRESET;                    //
> Activate watchdog
>     WDFEED = 0xAA; WDFEED = 0x55;
> 
> I must have misunderstood the WD functionality. What
> am I doing wrong? 
> In the above code the watchdog should not trigger
> until 5 minutes 
> elapsed so even if a vector should be wrong the code
> that follow should 
> run for a while but as soon as I write to the WDMOD
> register I get a hang.
> 
> /Ake
> 
> -- 
>  ---
> Ake Hedman (YAP - Yet Another Programmer)
> eurosource, Brattbergavägen 17, 820 50 LOS, Sweden
> Phone: (46) 657 413430 Cellular: (46) 73 84 84 102
> Company home: http://www.eurosource.se      
> Kryddor/Te/Kaffe: http://www.brattberg.com
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Re: [lpc2000] Re: Problem with watchdog

2005-12-07 by Ake Hedman, eurosource

Hi Danish,

Not dumb a *very good* suggestion. Not  dumb or not matters now. I will 
try every suggestion at this stage... Everyone who have done some 
projects know the feeling. Everything in place. The product  ready to be 
sent to the customer.... Just have to enable that tiny little thing 
also.....  ;-)

Back to work!
/Ake

dr_danish_ali wrote:

> Ok Ake, here's my dumb suggestion:
>
> Try enabling the watchdog, but just to interrupt not reset?
> You'll need an interrupt handler / VIC channel to do it - can you 
> spare one?
> That ISR need just raise a flag for now.
>
> Once the watchdog is fed and running happily, you might then be able 
> to enable resets on
> it.
>
> Hope this helps,
> Danish
>
> --- In lpc2000@yahoogroups.com, "Ake Hedman, eurosource" <akhe@b...> 
> wrote:
> >
> > I am still trying to solve my problems with the watchdog.
> >
> > I have now scaled away most stuff of my application and can see that 
> the
> > problem occurs when either of three interrupts occur (UART0/UART1/I2C0)
> > in the system. Without the watchdog everything works fine but if I
> > enable the watchdog everything crashes. I have tried to just enable and
> > trig one of the interrupts in turn but the situation is the same.
> >
> > I'm totally out of clues at the moment so any (also things that 
> might be
> > considered dumb) are very welcome.
> >
> > Regards
> > /Ake
>
>
>
>
>
> SPONSORED LINKS
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-- 
 ---
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eurosource, Brattbergavägen 17, 820 50 LOS, Sweden
Phone: (46) 657 413430 Cellular: (46) 73 84 84 102
Company home: http://www.eurosource.se      
Kryddor/Te/Kaffe: http://www.brattberg.com
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Automated home: http://www.vscp.org



[Non-text portions of this message have been removed]

Re: [lpc2000] Problem with watchdog

2005-12-07 by Ake Hedman, eurosource

Hi,

thanks for the suggestions. Also well worth a try. I will report my 
findings back.

I would like to thank you and everyone else who have responded to this 
problem. Your suggestions, questions are very valuable and I hope I can 
give something back in the future.

/Ake

3gpabko wrote:

> Hi there,
> there is a note in the UM about the feeding sequence
> of the PLL which says that the writing of 0xAA and
> then 0x55 must be two consecutive VPB cycles. No
> interrupts between them. For the WDT the text is
> different it says that after feeding 0xAA "...the next
> operation in the Watchdog register space should be a
> WRITE (0x55) to the WDFEED register otherwise the
> Watchdog is triggered."
>
> May be the dog doesn't like to be interrupted when
> feeding.
>  
> Regards
>
> --- "Ake Hedman, eurosource" <akhe@brattberg.com>
> wrote:
>
> > Hi all.
> >
> > I am trying to enable the watchdog but the result is
> > a total hang of the
> > board. Not even the bootloader is possible to reach
> > after the crash and
> > I have to reapply power with P0.14 low to get access
> > to the botloader
> > again. Reset is not enough.
> >
> > The code to initialize the watchdog is
> >
> >     // initialize the watchdog timer
> >     WDTC = 0xffffffff; // 15000000;                
> >       // One second
> > = 15000000
> >     WDMOD = WDEN | WDRESET;                    //
> > Activate watchdog
> >     WDFEED = 0xAA; WDFEED = 0x55;
> >
> > I must have misunderstood the WD functionality. What
> > am I doing wrong?
> > In the above code the watchdog should not trigger
> > until 5 minutes
> > elapsed so even if a vector should be wrong the code
> > that follow should
> > run for a while but as soon as I write to the WDMOD
> > register I get a hang.
> >
> > /Ake
> >
> > --
> >  ---
> > Ake Hedman (YAP - Yet Another Programmer)
> > eurosource, Brattbergavägen 17, 820 50 LOS, Sweden
> > Phone: (46) 657 413430 Cellular: (46) 73 84 84 102
> > Company home: http://www.eurosource.se     
> > Kryddor/Te/Kaffe: http://www.brattberg.com
> > Personal homepage: http://www.eurosource.se/akhe
> > Automated home: http://www.vscp.org
> >
> >
> >
>
>
>
>            
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-- 
 ---
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eurosource, Brattbergavägen 17, 820 50 LOS, Sweden
Phone: (46) 657 413430 Cellular: (46) 73 84 84 102
Company home: http://www.eurosource.se      
Kryddor/Te/Kaffe: http://www.brattberg.com
Personal homepage: http://www.eurosource.se/akhe
Automated home: http://www.vscp.org



[Non-text portions of this message have been removed]

Re: [lpc2000] Re: Problem with watchdog

2005-12-07 by Ake Hedman, eurosource

WD story update

I changed the code to have the watchdog raising an IRQ instead of a 
RESET.  I initialize stuff and then go in in a while loop.

1.) With interrupts enabled but no interrupt channel active this will 
not trigger the watchdog. Why?

2.) With one of the interrupt channels active ( UART0 writing some 
characters ) the watchdog works. Without a dog feed the watchdog is 
triggered and with a feed it runs fine. However what I initialize WDTC 
with does to seem to matter. I always get about 4 ms period when I 
toggle a pin in the WD interrupt (60MHz clock).

Is this behaviour recognized by anyone? Please!

BTW the chip is LPC2138

/Ake


dr_danish_ali wrote:

> Ok Ake, here's my dumb suggestion:
>
> Try enabling the watchdog, but just to interrupt not reset?
> You'll need an interrupt handler / VIC channel to do it - can you 
> spare one?
> That ISR need just raise a flag for now.
>
> Once the watchdog is fed and running happily, you might then be able 
> to enable resets on
> it.
>
> Hope this helps,
> Danish
>
> --- In lpc2000@yahoogroups.com, "Ake Hedman, eurosource" <akhe@b...> 
> wrote:
> >
> > I am still trying to solve my problems with the watchdog.
> >
> > I have now scaled away most stuff of my application and can see that 
> the
> > problem occurs when either of three interrupts occur (UART0/UART1/I2C0)
> > in the system. Without the watchdog everything works fine but if I
> > enable the watchdog everything crashes. I have tried to just enable and
> > trig one of the interrupts in turn but the situation is the same.
> >
> > I'm totally out of clues at the moment so any (also things that 
> might be
> > considered dumb) are very welcome.
> >
> > Regards
> > /Ake
>
>
>
>
>
> SPONSORED LINKS
> Microprocessor 
> <http://groups.yahoo.com/gads?t=ms&k=Microprocessor&w1=Microprocessor&w2=Microcontrollers&w3=Pic+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=tsVC-J9hJ5qyXg0WPR0l6g> 
> 	Microcontrollers 
> <http://groups.yahoo.com/gads?t=ms&k=Microcontrollers&w1=Microprocessor&w2=Microcontrollers&w3=Pic+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=DvJVNqC_pqRTm8Xq01nxwg> 
> 	Pic microcontrollers 
> <http://groups.yahoo.com/gads?t=ms&k=Pic+microcontrollers&w1=Microprocessor&w2=Microcontrollers&w3=Pic+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=TpkoX4KofDJ7c6LyBvUqVQ> 
>
> 8051 microprocessor 
> <http://groups.yahoo.com/gads?t=ms&k=8051+microprocessor&w1=Microprocessor&w2=Microcontrollers&w3=Pic+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=1Ipf1Fjfbd_HVIlekkDP-A> 
>
>
>
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-- 
 ---
Ake Hedman (YAP - Yet Another Programmer)
eurosource, Brattbergavägen 17, 820 50 LOS, Sweden
Phone: (46) 657 413430 Cellular: (46) 73 84 84 102
Company home: http://www.eurosource.se      
Kryddor/Te/Kaffe: http://www.brattberg.com
Personal homepage: http://www.eurosource.se/akhe
Automated home: http://www.vscp.org



[Non-text portions of this message have been removed]

Re: Problem with watchdog

2005-12-08 by brendanmurphy37

Ake,

I can almost feel your frustration: we've all been there!

I'm very interested in the outcome of this, as our own task for next 
week is to get the watchdog working on our own LPC2134-based system. 

I'm a bit surprised that no one has volunteered some working code. 
Surely someone out there is using this?

Unfortunately, as we haven't got there yet, I've nothing specific to 
suggest, other than a general strategy of getting something simple 
working first, and then building up to where you are. For example:

1. As simple as possible startup, initialisation (all peripherals 
disabled, all interrupts off etc.) and an application that 
initialises the watchdog and uses GPIO to signal what it's doing (and 
maybe reads to indicate whether or not the watchdog should be fed). 
In other words, the simplest possible program with a working 
watchdog. 

2. Same program, but with your normal initialisation and setup code, 
added incrementally. Still working?

3. Compare and contrast with your real application, particularly in 
how peripherals, interrupts etc. are managed.

In other words, get something simple working first, and build up from 
there. It'll take time, but maybe less time then starting from a 
larger system that doesn't work.

Hopefully, somewhere along the line, all will become obvious.

By the way, are you running your code using an emulator connected? 
I've seen strange behaviour in the past with watchdogs enabled. Try 
running stand-alone, if you haven't done so already.

As a final suggestion, based on what you say below, I'd look very 
carefully at every location interrupts are enabled/disabled (at the 
peripheral level, at the VIC and at the CPSR). Also at your startup 
and IRQ dispatch code. Maybe the processor is resetting and re-
initialising stuff without you realising? maybe throwing an exception 
you haven't noticed?

As a final comment: 'though no doubt it feels like it, it's not time 
wasted: you'll know way more about the watchdog and processor at the 
end of all this then when you started.

Good luck!

Brendan


--- In lpc2000@yahoogroups.com, "Ake Hedman, eurosource" <akhe@b...> 
wrote:
>
> WD story update
> 
> I changed the code to have the watchdog raising an IRQ instead of a 
> RESET.  I initialize stuff and then go in in a while loop.
> 
> 1.) With interrupts enabled but no interrupt channel active this 
will 
> not trigger the watchdog. Why?
> 
> 2.) With one of the interrupt channels active ( UART0 writing some 
> characters ) the watchdog works. Without a dog feed the watchdog is 
> triggered and with a feed it runs fine. However what I initialize 
WDTC 
> with does to seem to matter. I always get about 4 ms period when I 
> toggle a pin in the WD interrupt (60MHz clock).
> 
> Is this behaviour recognized by anyone? Please!
> 
> BTW the chip is LPC2138
> 
> /Ake
> 
> 
> dr_danish_ali wrote:
> 
> > Ok Ake, here's my dumb suggestion:
> >
> > Try enabling the watchdog, but just to interrupt not reset?
> > You'll need an interrupt handler / VIC channel to do it - can you 
> > spare one?
> > That ISR need just raise a flag for now.
> >
> > Once the watchdog is fed and running happily, you might then be 
able 
> > to enable resets on
> > it.
> >
> > Hope this helps,
> > Danish
> >
> > --- In lpc2000@yahoogroups.com, "Ake Hedman, eurosource" 
<akhe@b...> 
> > wrote:
> > >
> > > I am still trying to solve my problems with the watchdog.
> > >
> > > I have now scaled away most stuff of my application and can see 
that 
> > the
> > > problem occurs when either of three interrupts occur 
(UART0/UART1/I2C0)
> > > in the system. Without the watchdog everything works fine but 
if I
> > > enable the watchdog everything crashes. I have tried to just 
enable and
> > > trig one of the interrupts in turn but the situation is the 
same.
> > >
> > > I'm totally out of clues at the moment so any (also things that 
> > might be
> > > considered dumb) are very welcome.
> > >
> > > Regards
> > > /Ake
> >
> >
> >
> >
> >
> > SPONSORED LINKS
> > Microprocessor 
> > <http://groups.yahoo.com/gads?
t=ms&k=Microprocessor&w1=Microprocessor&w2=Microcontrollers&w3=Pic+mic
rocontrollers&w4=8051+microprocessor&c=4&s=93&.sig=tsVC-
J9hJ5qyXg0WPR0l6g> 
> > 	Microcontrollers 
> > <http://groups.yahoo.com/gads?
t=ms&k=Microcontrollers&w1=Microprocessor&w2=Microcontrollers&w3=Pic+m
icrocontrollers&w4=8051+microprocessor&c=4&s=93&.sig=DvJVNqC_pqRTm8Xq0
1nxwg> 
> > 	Pic microcontrollers 
> > <http://groups.yahoo.com/gads?
t=ms&k=Pic+microcontrollers&w1=Microprocessor&w2=Microcontrollers&w3=P
ic+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=TpkoX4KofDJ7c
6LyBvUqVQ> 
> >
> > 8051 microprocessor 
> > <http://groups.yahoo.com/gads?
t=ms&k=8051+microprocessor&w1=Microprocessor&w2=Microcontrollers&w3=Pi
c+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=1Ipf1Fjfbd_HVI
lekkDP-A> 
> >
> >
> >
> > ------------------------------------------------------------------
------
> > YAHOO! GROUPS LINKS
> >
> >     *  Visit your group "lpc2000
> >       <http://groups.yahoo.com/group/lpc2000>" on the web.
> >        
> >     *  To unsubscribe from this group, send an email to:
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subject=Unsubscribe>
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> >       Service <http://docs.yahoo.com/info/terms/>.
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> > ------------------------------------------------------------------
------
Show quoted textHide quoted text
> >
> 
> 
> -- 
>  ---
> Ake Hedman (YAP - Yet Another Programmer)
> eurosource, Brattbergavägen 17, 820 50 LOS, Sweden
> Phone: (46) 657 413430 Cellular: (46) 73 84 84 102
> Company home: http://www.eurosource.se      
> Kryddor/Te/Kaffe: http://www.brattberg.com
> Personal homepage: http://www.eurosource.se/akhe
> Automated home: http://www.vscp.org
> 
> 
> 
> [Non-text portions of this message have been removed]
>

Re: [lpc2000] Re: Problem with watchdog

2005-12-08 by Ake Hedman, eurosource

Thanks Brendan,

This is the right approach surely. I'm at that state now and have no 
other alternative then to back a bit and go through this "the right 
way". I just have myself to blame. Have used watchdogs for many years on 
PIC, AVR and other processors and expected no problem there except for 
the usual forgetting to feed it in certain places. Oh well it's my first 
project on this processor family so this makes me learn useful stuff 
just as you write (just a bit hard to appreciate that right now ;-) ). 
Really need the watchdog to work in this application though so there is 
no shortcut.

I just debug using GPIO pins and one of the serial ports at the moment 
so there is no emulator connected now.

Thanks for your tips, suggestions and moral support. I report my 
findings back.
/Ake


brendanmurphy37 wrote:

>
> Ake,
>
> I can almost feel your frustration: we've all been there!
>
> I'm very interested in the outcome of this, as our own task for next
> week is to get the watchdog working on our own LPC2134-based system.
>
> I'm a bit surprised that no one has volunteered some working code.
> Surely someone out there is using this?
>
> Unfortunately, as we haven't got there yet, I've nothing specific to
> suggest, other than a general strategy of getting something simple
> working first, and then building up to where you are. For example:
>
> 1. As simple as possible startup, initialisation (all peripherals
> disabled, all interrupts off etc.) and an application that
> initialises the watchdog and uses GPIO to signal what it's doing (and
> maybe reads to indicate whether or not the watchdog should be fed).
> In other words, the simplest possible program with a working
> watchdog.
>
> 2. Same program, but with your normal initialisation and setup code,
> added incrementally. Still working?
>
> 3. Compare and contrast with your real application, particularly in
> how peripherals, interrupts etc. are managed.
>
> In other words, get something simple working first, and build up from
> there. It'll take time, but maybe less time then starting from a
> larger system that doesn't work.
>
> Hopefully, somewhere along the line, all will become obvious.
>
> By the way, are you running your code using an emulator connected?
> I've seen strange behaviour in the past with watchdogs enabled. Try
> running stand-alone, if you haven't done so already.
>
> As a final suggestion, based on what you say below, I'd look very
> carefully at every location interrupts are enabled/disabled (at the
> peripheral level, at the VIC and at the CPSR). Also at your startup
> and IRQ dispatch code. Maybe the processor is resetting and re-
> initialising stuff without you realising? maybe throwing an exception
> you haven't noticed?
>
> As a final comment: 'though no doubt it feels like it, it's not time
> wasted: you'll know way more about the watchdog and processor at the
> end of all this then when you started.
>
> Good luck!
>
> Brendan
>
>
> --- In lpc2000@yahoogroups.com, "Ake Hedman, eurosource" <akhe@b...>
> wrote:
> >
> > WD story update
> >
> > I changed the code to have the watchdog raising an IRQ instead of a
> > RESET.  I initialize stuff and then go in in a while loop.
> >
> > 1.) With interrupts enabled but no interrupt channel active this
> will
> > not trigger the watchdog. Why?
> >
> > 2.) With one of the interrupt channels active ( UART0 writing some
> > characters ) the watchdog works. Without a dog feed the watchdog is
> > triggered and with a feed it runs fine. However what I initialize
> WDTC
> > with does to seem to matter. I always get about 4 ms period when I
> > toggle a pin in the WD interrupt (60MHz clock).
> >
> > Is this behaviour recognized by anyone? Please!
> >
> > BTW the chip is LPC2138
> >
> > /Ake
> >
> >
> > dr_danish_ali wrote:
> >
> > > Ok Ake, here's my dumb suggestion:
> > >
> > > Try enabling the watchdog, but just to interrupt not reset?
> > > You'll need an interrupt handler / VIC channel to do it - can you
> > > spare one?
> > > That ISR need just raise a flag for now.
> > >
> > > Once the watchdog is fed and running happily, you might then be
> able
> > > to enable resets on
> > > it.
> > >
> > > Hope this helps,
> > > Danish
> > >
> > > --- In lpc2000@yahoogroups.com, "Ake Hedman, eurosource"
> <akhe@b...>
> > > wrote:
> > > >
> > > > I am still trying to solve my problems with the watchdog.
> > > >
> > > > I have now scaled away most stuff of my application and can see
> that
> > > the
> > > > problem occurs when either of three interrupts occur
> (UART0/UART1/I2C0)
> > > > in the system. Without the watchdog everything works fine but
> if I
> > > > enable the watchdog everything crashes. I have tried to just
> enable and
> > > > trig one of the interrupts in turn but the situation is the
> same.
> > > >
> > > > I'm totally out of clues at the moment so any (also things that
> > > might be
> > > > considered dumb) are very welcome.
> > > >
> > > > Regards
> > > > /Ake
> > >
> > >
> > >
> > >
> > >
> > > SPONSORED LINKS
> > > Microprocessor
> > > <http://groups.yahoo.com/gads?
> t=ms&k=Microprocessor&w1=Microprocessor&w2=Microcontrollers&w3=Pic+mic
> rocontrollers&w4=8051+microprocessor&c=4&s=93&.sig=tsVC-
> J9hJ5qyXg0WPR0l6g>
> > >       Microcontrollers
> > > <http://groups.yahoo.com/gads?
> t=ms&k=Microcontrollers&w1=Microprocessor&w2=Microcontrollers&w3=Pic+m
> icrocontrollers&w4=8051+microprocessor&c=4&s=93&.sig=DvJVNqC_pqRTm8Xq0
> 1nxwg>
> > >       Pic microcontrollers
> > > <http://groups.yahoo.com/gads?
> t=ms&k=Pic+microcontrollers&w1=Microprocessor&w2=Microcontrollers&w3=P
> ic+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=TpkoX4KofDJ7c
> 6LyBvUqVQ>
> > >
> > > 8051 microprocessor
> > > <http://groups.yahoo.com/gads?
> t=ms&k=8051+microprocessor&w1=Microprocessor&w2=Microcontrollers&w3=Pi
> c+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=1Ipf1Fjfbd_HVI
> lekkDP-A>
> > >
> > >
> > >
> > > ------------------------------------------------------------------
> ------
> > > YAHOO! GROUPS LINKS
> > >
> > >     *  Visit your group "lpc2000
> > >       <http://groups.yahoo.com/group/lpc2000>" on the web.
> > >       
> > >     *  To unsubscribe from this group, send an email to:
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> subject=Unsubscribe>
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> > >
> > >
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> ------
> > >
> >
> >
> > --
> >  ---
> > Ake Hedman (YAP - Yet Another Programmer)
> > eurosource, Brattbergavägen 17, 820 50 LOS, Sweden
> > Phone: (46) 657 413430 Cellular: (46) 73 84 84 102
> > Company home: http://www.eurosource.se     
> > Kryddor/Te/Kaffe: http://www.brattberg.com
> > Personal homepage: http://www.eurosource.se/akhe
> > Automated home: http://www.vscp.org
> >
> >
> >
> > [Non-text portions of this message have been removed]
> >
>
>
>
>
>
> ------------------------------------------------------------------------
> YAHOO! GROUPS LINKS
>
>     *  Visit your group "lpc2000
>       <http://groups.yahoo.com/group/lpc2000>" on the web.
>        
>     *  To unsubscribe from this group, send an email to:
>        lpc2000-unsubscribe@yahoogroups.com
>       <mailto:lpc2000-unsubscribe@yahoogroups.com?subject=Unsubscribe>
>        
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>       Service <http://docs.yahoo.com/info/terms/>.
>
>
> ------------------------------------------------------------------------
>


-- 
 ---
Ake Hedman (YAP - Yet Another Programmer)
eurosource, Brattbergavägen 17, 820 50 LOS, Sweden
Phone: (46) 657 413430 Cellular: (46) 73 84 84 102
Company home: http://www.eurosource.se      
Kryddor/Te/Kaffe: http://www.brattberg.com
Personal homepage: http://www.eurosource.se/akhe
Automated home: http://www.vscp.org



[Non-text portions of this message have been removed]

Re: Problem with watchdog

2005-12-08 by brendanmurphy37

Ake,

Thanks for your comments.

I'm not sure if you want to hear this or not, but we've just put in 
support for the watchdog. It worked first time, with no problems. 
Code is below: two functions, one called as part of startup sequence, 
the other called from a watchdog task that's scheduled every second. 
If we spin in a loop locking out all other tasks, the system is reset 
as expected.

Our system has several sources of interrupt enabled (both UARTs, I2C 
etc.): it works regardless of what's happeneing elsewhere.

By the way, we use GCC 3.3.1 with -O2 to compile.

Regards
Brendan

=========================================
CODE STARTS HERE:

#define REG(addr) (*(volatile unsigned int *)(addr))

#define WDOG_BASE    (0xE0000000)
#define WDOG_WDMOD   (0xE0000000)
#define WDOG_WDTC    (0xE0000004)
#define WDOG_WDFEED  (0xE0000008)
#define WDOG_WDTV    (0xE000000C)

/* define basic watchdog timeout value as 100 ms */

#define	WATCH_TIMER_100MS (250000) /* 10 MHz / 4 is i/p clock */

/*
 * Configure and start watchdog
 */

static
void	watchdog_init(void)

{
  /* set the watchdog timer constant */

  REG(WDOG_WDTC) = WATCH_TIMER_100MS * (50); /* 5 seconds for now */

  /* set mode to reset on underflow */

  REG(WDOG_WDMOD) = 0x3;

  /* feed watchdog to start it off */

  REG(WDOG_WDFEED) = 0xaa;
  REG(WDOG_WDFEED) = 0x55;

  return;
}

/*
 * Feed the watchdog to prevent us from being reset
 */

void	HwWatchdogFeed(void)

{
  /* write the magic sequence to keep the dog happy */

  REG(WDOG_WDFEED) = 0xaa;
  REG(WDOG_WDFEED) = 0x55;

  return;
}

END OF CODE
========================================

--- In lpc2000@yahoogroups.com, "Ake Hedman, eurosource" <akhe@b...> 
wrote:
>
> Thanks Brendan,
> 
> This is the right approach surely. I'm at that state now and have 
no 
> other alternative then to back a bit and go through this "the right 
> way". I just have myself to blame. Have used watchdogs for many 
years on 
> PIC, AVR and other processors and expected no problem there except 
for 
> the usual forgetting to feed it in certain places. Oh well it's my 
first 
> project on this processor family so this makes me learn useful 
stuff 
> just as you write (just a bit hard to appreciate that right now ;-
) ). 
> Really need the watchdog to work in this application though so 
there is 
> no shortcut.
> 
> I just debug using GPIO pins and one of the serial ports at the 
moment 
> so there is no emulator connected now.
> 
> Thanks for your tips, suggestions and moral support. I report my 
> findings back.
> /Ake
> 
> 
> brendanmurphy37 wrote:
> 
> >
> > Ake,
> >
> > I can almost feel your frustration: we've all been there!
> >
> > I'm very interested in the outcome of this, as our own task for 
next
> > week is to get the watchdog working on our own LPC2134-based 
system.
> >
> > I'm a bit surprised that no one has volunteered some working code.
> > Surely someone out there is using this?
> >
> > Unfortunately, as we haven't got there yet, I've nothing specific 
to
> > suggest, other than a general strategy of getting something simple
> > working first, and then building up to where you are. For example:
> >
> > 1. As simple as possible startup, initialisation (all peripherals
> > disabled, all interrupts off etc.) and an application that
> > initialises the watchdog and uses GPIO to signal what it's doing 
(and
> > maybe reads to indicate whether or not the watchdog should be 
fed).
> > In other words, the simplest possible program with a working
> > watchdog.
> >
> > 2. Same program, but with your normal initialisation and setup 
code,
> > added incrementally. Still working?
> >
> > 3. Compare and contrast with your real application, particularly 
in
> > how peripherals, interrupts etc. are managed.
> >
> > In other words, get something simple working first, and build up 
from
> > there. It'll take time, but maybe less time then starting from a
> > larger system that doesn't work.
> >
> > Hopefully, somewhere along the line, all will become obvious.
> >
> > By the way, are you running your code using an emulator connected?
> > I've seen strange behaviour in the past with watchdogs enabled. 
Try
> > running stand-alone, if you haven't done so already.
> >
> > As a final suggestion, based on what you say below, I'd look very
> > carefully at every location interrupts are enabled/disabled (at 
the
> > peripheral level, at the VIC and at the CPSR). Also at your 
startup
> > and IRQ dispatch code. Maybe the processor is resetting and re-
> > initialising stuff without you realising? maybe throwing an 
exception
> > you haven't noticed?
> >
> > As a final comment: 'though no doubt it feels like it, it's not 
time
> > wasted: you'll know way more about the watchdog and processor at 
the
> > end of all this then when you started.
> >
> > Good luck!
> >
> > Brendan
> >
> >
> > --- In lpc2000@yahoogroups.com, "Ake Hedman, eurosource" 
<akhe@b...>
> > wrote:
> > >
> > > WD story update
> > >
> > > I changed the code to have the watchdog raising an IRQ instead 
of a
> > > RESET.  I initialize stuff and then go in in a while loop.
> > >
> > > 1.) With interrupts enabled but no interrupt channel active this
> > will
> > > not trigger the watchdog. Why?
> > >
> > > 2.) With one of the interrupt channels active ( UART0 writing 
some
> > > characters ) the watchdog works. Without a dog feed the 
watchdog is
> > > triggered and with a feed it runs fine. However what I 
initialize
> > WDTC
> > > with does to seem to matter. I always get about 4 ms period 
when I
> > > toggle a pin in the WD interrupt (60MHz clock).
> > >
> > > Is this behaviour recognized by anyone? Please!
> > >
> > > BTW the chip is LPC2138
> > >
> > > /Ake
> > >
> > >
> > > dr_danish_ali wrote:
> > >
> > > > Ok Ake, here's my dumb suggestion:
> > > >
> > > > Try enabling the watchdog, but just to interrupt not reset?
> > > > You'll need an interrupt handler / VIC channel to do it - can 
you
> > > > spare one?
> > > > That ISR need just raise a flag for now.
> > > >
> > > > Once the watchdog is fed and running happily, you might then 
be
> > able
> > > > to enable resets on
> > > > it.
> > > >
> > > > Hope this helps,
> > > > Danish
> > > >
> > > > --- In lpc2000@yahoogroups.com, "Ake Hedman, eurosource"
> > <akhe@b...>
> > > > wrote:
> > > > >
> > > > > I am still trying to solve my problems with the watchdog.
> > > > >
> > > > > I have now scaled away most stuff of my application and can 
see
> > that
> > > > the
> > > > > problem occurs when either of three interrupts occur
> > (UART0/UART1/I2C0)
> > > > > in the system. Without the watchdog everything works fine 
but
> > if I
> > > > > enable the watchdog everything crashes. I have tried to just
> > enable and
> > > > > trig one of the interrupts in turn but the situation is the
> > same.
> > > > >
> > > > > I'm totally out of clues at the moment so any (also things 
that
> > > > might be
> > > > > considered dumb) are very welcome.
> > > > >
> > > > > Regards
> > > > > /Ake
> > > >
> > > >
> > > >
> > > >
> > > >
> > > > SPONSORED LINKS
> > > > Microprocessor
> > > > <http://groups.yahoo.com/gads?
> > 
t=ms&k=Microprocessor&w1=Microprocessor&w2=Microcontrollers&w3=Pic+mic
> > rocontrollers&w4=8051+microprocessor&c=4&s=93&.sig=tsVC-
> > J9hJ5qyXg0WPR0l6g>
> > > >       Microcontrollers
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> > 
t=ms&k=Microcontrollers&w1=Microprocessor&w2=Microcontrollers&w3=Pic+m
> > 
icrocontrollers&w4=8051+microprocessor&c=4&s=93&.sig=DvJVNqC_pqRTm8Xq0
> > 1nxwg>
> > > >       Pic microcontrollers
> > > > <http://groups.yahoo.com/gads?
> > 
t=ms&k=Pic+microcontrollers&w1=Microprocessor&w2=Microcontrollers&w3=P
> > 
ic+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=TpkoX4KofDJ7c
> > 6LyBvUqVQ>
> > > >
> > > > 8051 microprocessor
> > > > <http://groups.yahoo.com/gads?
> > 
t=ms&k=8051+microprocessor&w1=Microprocessor&w2=Microcontrollers&w3=Pi
> > 
c+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=1Ipf1Fjfbd_HVI
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Re: [lpc2000] Re: Problem with watchdog

2005-12-08 by Ake Hedman, eurosource

Brenda*n,*

thanks. It's really good to here that.  Even if 99.999% of the problems 
comes from the code we write ourselves it is still nice to take away 
that 0.0001% that comes from problems in hardware.

I'm in the process of doing a new test project at the moment to try to 
trace this down under a more controlled environment.

Thanks for taking the time to sharing this info. Much appreciated!

Cheers
/Ake

brendanmurphy37 wrote:

>
> Ake,
>
> Thanks for your comments.
>
> I'm not sure if you want to hear this or not, but we've just put in
> support for the watchdog. It worked first time, with no problems.
> Code is below: two functions, one called as part of startup sequence,
> the other called from a watchdog task that's scheduled every second.
> If we spin in a loop locking out all other tasks, the system is reset
> as expected.
>
> Our system has several sources of interrupt enabled (both UARTs, I2C
> etc.): it works regardless of what's happeneing elsewhere.
>
> By the way, we use GCC 3.3.1 with -O2 to compile.
>
> Regards
> Brendan
>
> =========================================
> CODE STARTS HERE:
>
> #define REG(addr) (*(volatile unsigned int *)(addr))
>
> #define WDOG_BASE    (0xE0000000)
> #define WDOG_WDMOD   (0xE0000000)
> #define WDOG_WDTC    (0xE0000004)
> #define WDOG_WDFEED  (0xE0000008)
> #define WDOG_WDTV    (0xE000000C)
>
> /* define basic watchdog timeout value as 100 ms */
>
> #define      WATCH_TIMER_100MS (250000) /* 10 MHz / 4 is i/p clock */
>
> /*
> * Configure and start watchdog
> */
>
> static
> void      watchdog_init(void)
>
> {
>   /* set the watchdog timer constant */
>
>   REG(WDOG_WDTC) = WATCH_TIMER_100MS * (50); /* 5 seconds for now */
>
>   /* set mode to reset on underflow */
>
>   REG(WDOG_WDMOD) = 0x3;
>
>   /* feed watchdog to start it off */
>
>   REG(WDOG_WDFEED) = 0xaa;
>   REG(WDOG_WDFEED) = 0x55;
>
>   return;
> }
>
> /*
> * Feed the watchdog to prevent us from being reset
> */
>
> void      HwWatchdogFeed(void)
>
> {
>   /* write the magic sequence to keep the dog happy */
>
>   REG(WDOG_WDFEED) = 0xaa;
>   REG(WDOG_WDFEED) = 0x55;
>
>   return;
> }
>
> END OF CODE
> ========================================
>
> --- In lpc2000@yahoogroups.com, "Ake Hedman, eurosource" <akhe@b...>
> wrote:
> >
> > Thanks Brendan,
> >
> > This is the right approach surely. I'm at that state now and have
> no
> > other alternative then to back a bit and go through this "the right
> > way". I just have myself to blame. Have used watchdogs for many
> years on
> > PIC, AVR and other processors and expected no problem there except
> for
> > the usual forgetting to feed it in certain places. Oh well it's my
> first
> > project on this processor family so this makes me learn useful
> stuff
> > just as you write (just a bit hard to appreciate that right now ;-
> ) ).
> > Really need the watchdog to work in this application though so
> there is
> > no shortcut.
> >
> > I just debug using GPIO pins and one of the serial ports at the
> moment
> > so there is no emulator connected now.
> >
> > Thanks for your tips, suggestions and moral support. I report my
> > findings back.
> > /Ake
> >
> >
> > brendanmurphy37 wrote:
> >
> > >
> > > Ake,
> > >
> > > I can almost feel your frustration: we've all been there!
> > >
> > > I'm very interested in the outcome of this, as our own task for
> next
> > > week is to get the watchdog working on our own LPC2134-based
> system.
> > >
> > > I'm a bit surprised that no one has volunteered some working code.
> > > Surely someone out there is using this?
> > >
> > > Unfortunately, as we haven't got there yet, I've nothing specific
> to
> > > suggest, other than a general strategy of getting something simple
> > > working first, and then building up to where you are. For example:
> > >
> > > 1. As simple as possible startup, initialisation (all peripherals
> > > disabled, all interrupts off etc.) and an application that
> > > initialises the watchdog and uses GPIO to signal what it's doing
> (and
> > > maybe reads to indicate whether or not the watchdog should be
> fed).
> > > In other words, the simplest possible program with a working
> > > watchdog.
> > >
> > > 2. Same program, but with your normal initialisation and setup
> code,
> > > added incrementally. Still working?
> > >
> > > 3. Compare and contrast with your real application, particularly
> in
> > > how peripherals, interrupts etc. are managed.
> > >
> > > In other words, get something simple working first, and build up
> from
> > > there. It'll take time, but maybe less time then starting from a
> > > larger system that doesn't work.
> > >
> > > Hopefully, somewhere along the line, all will become obvious.
> > >
> > > By the way, are you running your code using an emulator connected?
> > > I've seen strange behaviour in the past with watchdogs enabled.
> Try
> > > running stand-alone, if you haven't done so already.
> > >
> > > As a final suggestion, based on what you say below, I'd look very
> > > carefully at every location interrupts are enabled/disabled (at
> the
> > > peripheral level, at the VIC and at the CPSR). Also at your
> startup
> > > and IRQ dispatch code. Maybe the processor is resetting and re-
> > > initialising stuff without you realising? maybe throwing an
> exception
> > > you haven't noticed?
> > >
> > > As a final comment: 'though no doubt it feels like it, it's not
> time
> > > wasted: you'll know way more about the watchdog and processor at
> the
> > > end of all this then when you started.
> > >
> > > Good luck!
> > >
> > > Brendan
> > >
> > >
> > > --- In lpc2000@yahoogroups.com, "Ake Hedman, eurosource"
> <akhe@b...>
> > > wrote:
> > > >
> > > > WD story update
> > > >
> > > > I changed the code to have the watchdog raising an IRQ instead
> of a
> > > > RESET.  I initialize stuff and then go in in a while loop.
> > > >
> > > > 1.) With interrupts enabled but no interrupt channel active this
> > > will
> > > > not trigger the watchdog. Why?
> > > >
> > > > 2.) With one of the interrupt channels active ( UART0 writing
> some
> > > > characters ) the watchdog works. Without a dog feed the
> watchdog is
> > > > triggered and with a feed it runs fine. However what I
> initialize
> > > WDTC
> > > > with does to seem to matter. I always get about 4 ms period
> when I
> > > > toggle a pin in the WD interrupt (60MHz clock).
> > > >
> > > > Is this behaviour recognized by anyone? Please!
> > > >
> > > > BTW the chip is LPC2138
> > > >
> > > > /Ake
> > > >
> > > >
> > > > dr_danish_ali wrote:
> > > >
> > > > > Ok Ake, here's my dumb suggestion:
> > > > >
> > > > > Try enabling the watchdog, but just to interrupt not reset?
> > > > > You'll need an interrupt handler / VIC channel to do it - can
> you
> > > > > spare one?
> > > > > That ISR need just raise a flag for now.
> > > > >
> > > > > Once the watchdog is fed and running happily, you might then
> be
> > > able
> > > > > to enable resets on
> > > > > it.
> > > > >
> > > > > Hope this helps,
> > > > > Danish
> > > > >
> > > > > --- In lpc2000@yahoogroups.com, "Ake Hedman, eurosource"
> > > <akhe@b...>
> > > > > wrote:
> > > > > >
> > > > > > I am still trying to solve my problems with the watchdog.
> > > > > >
> > > > > > I have now scaled away most stuff of my application and can
> see
> > > that
> > > > > the
> > > > > > problem occurs when either of three interrupts occur
> > > (UART0/UART1/I2C0)
> > > > > > in the system. Without the watchdog everything works fine
> but
> > > if I
> > > > > > enable the watchdog everything crashes. I have tried to just
> > > enable and
> > > > > > trig one of the interrupts in turn but the situation is the
> > > same.
> > > > > >
> > > > > > I'm totally out of clues at the moment so any (also things
> that
> > > > > might be
> > > > > > considered dumb) are very welcome.
> > > > > >
> > > > > > Regards
> > > > > > /Ake
> > > > >
> > > > >
> > > > >
> > > > >
> > > > >
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> > > rocontrollers&w4=8051+microprocessor&c=4&s=93&.sig=tsVC-
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> > >
> t=ms&k=Microcontrollers&w1=Microprocessor&w2=Microcontrollers&w3=Pic+m
> > >
> icrocontrollers&w4=8051+microprocessor&c=4&s=93&.sig=DvJVNqC_pqRTm8Xq0
> > > 1nxwg>
> > > > >       Pic microcontrollers
> > > > > <http://groups.yahoo.com/gads?
> > >
> t=ms&k=Pic+microcontrollers&w1=Microprocessor&w2=Microcontrollers&w3=P
> > >
> ic+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=TpkoX4KofDJ7c
> > > 6LyBvUqVQ>
> > > > >
> > > > > 8051 microprocessor
> > > > > <http://groups.yahoo.com/gads?
> > >
> t=ms&k=8051+microprocessor&w1=Microprocessor&w2=Microcontrollers&w3=Pi
> > >
> c+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=1Ipf1Fjfbd_HVI
> > > lekkDP-A>
> > > > >
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> > eurosource, Brattbergavägen 17, 820 50 LOS, Sweden
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-- 
 ---
Ake Hedman (YAP - Yet Another Programmer)
eurosource, Brattbergavägen 17, 820 50 LOS, Sweden
Phone: (46) 657 413430 Cellular: (46) 73 84 84 102
Company home: http://www.eurosource.se      
Kryddor/Te/Kaffe: http://www.brattberg.com
Personal homepage: http://www.eurosource.se/akhe
Automated home: http://www.vscp.org



[Non-text portions of this message have been removed]

Re: [lpc2000] Re: Problem with watchdog

2005-12-09 by Robert Adsett

At 10:58 AM 12/8/05 +0100, Ake Hedman, eurosource wrote:
>This is the right approach surely. I'm at that state now and have no
>other alternative then to back a bit and go through this "the right
>way". I just have myself to blame. Have used watchdogs for many years on
>PIC, AVR and other processors and expected no problem there except for
>the usual forgetting to feed it in certain places. Oh well it's my first
>project on this processor family so this makes me learn useful stuff
>just as you write (just a bit hard to appreciate that right now ;-) ).
>Really need the watchdog to work in this application though so there is
>no shortcut.

One thought that occurs to me, and I have no idea whether it is an issue 
with this processor, is that some watchdogs must be cleared before they are 
enabled or you run the risk of them firing as soon as you enable 
them.  Whether or not they do depends on when you start them and how the 
registers initialize etc...

Robert

" 'Freedom' has no meaning of itself.  There are always restrictions,   be 
they legal, genetic, or physical.  If you don't believe me, try to chew a 
radio signal. "  -- Kelvin Throop, III
http://www.aeolusdevelopment.com/

Re: Problem with watchdog

2005-12-09 by Ken Wada

Basically, your method works fine...
UNTIL: you start adding interrupt service routines!

This is why:
void WDOG_pet()
{
WDFEED = 0xAA;
/*             Interrupt occurs here...> dog will NOT pet properly!!! 
***/
WDFEED = 0x55;
}

/**** example uses Keil compiler directives ***/
/********** The following is what I wound up doing, (gotta avoid that 
spurious interrupt issue with the ARM also!!! ***/

/**** The actual interface that everybody uses ***/
void WDOG_pet (void)
{
    SYSSWI_service (12,0,0,0);
}

/***** How the SYSSWI_service works, (based on SWI) ***/
unsigned SYSSWI_service (SYSSWI opcode, int id, void *pObj, unsigned 
_user1) __swi(12)
{
    switch (opcode)
    {
      case SYSSWI_WDOGPET:
        SYSSWI_watchDogPet ();
        break;
      ...
    }
    return (0);
}

/***** How the SYSSWI_watchDogPet () works ***/
static void SYSSWI_watchDogPet (void)
{
    ARM_disableFIQ ();                /* make sure FIQ is disabled     
     */
    WDFEED  = 0xAA;
    WDFEED  = 0x55;
    ARM_enableFIQ ();                 /* re-enable the FIQ             
     */
}

/***** The IRQ is automatically disabled by vectoring to the SWI...
however, you need to make the operation atomic with respect to FIQ, 
which is NOT disabled ***/

PUBLIC  ARM_disableFIQ?A ; interface is ARM mode

ARM_disableFIQ?A  PROC  CODE32
      MRS   R0,CPSR
      ORR   R0,R0,#0x0040                   ; Mask just the FIQ
      MSR   CPSR_c,R0
      BX    R14

      ENDP

PUBLIC  ARM_enableFIQ?A ; interface is ARM mode

ARM_enableFIQ?A  PROC  CODE32
      MRS   R0,CPSR
      BIC   R0,R0,#0x0040                   ; Enable just the FIQ
      MSR   CPSR_c,R0
      BX    R14

      ENDP
END


--- In lpc2000@yahoogroups.com, "Ake Hedman, eurosource" <akhe@b...> 
wrote:
>
> Hi all.
> 
> I am trying to enable the watchdog but the result is a total hang of 
the 
> board. Not even the bootloader is possible to reach after the crash 
and 
> I have to reapply power with P0.14 low to get access to the 
botloader 
> again. Reset is not enough.
> 
> The code to initialize the watchdog is
> 
>     // initialize the watchdog timer
>     WDTC = 0xffffffff; // 15000000;                        // One 
second 
> = 15000000
>     WDMOD = WDEN | WDRESET;                    // Activate watchdog
>     WDFEED = 0xAA; WDFEED = 0x55;
> 
> I must have misunderstood the WD functionality. What am I doing 
wrong? 
> In the above code the watchdog should not trigger until 5 minutes 
> elapsed so even if a vector should be wrong the code that follow 
should 
> run for a while but as soon as I write to the WDMOD register I get a 
hang.
Show quoted textHide quoted text
> 
> /Ake
> 
> -- 
>  ---
> Ake Hedman (YAP - Yet Another Programmer)
> eurosource, Brattbergavägen 17, 820 50 LOS, Sweden
> Phone: (46) 657 413430 Cellular: (46) 73 84 84 102
> Company home: http://www.eurosource.se      
> Kryddor/Te/Kaffe: http://www.brattberg.com
> Personal homepage: http://www.eurosource.se/akhe
> Automated home: http://www.vscp.org
>

Re: [lpc2000] Re: Problem with watchdog

2005-12-09 by Ake Hedman, eurosource

Robert Adsett wrote:

> At 10:58 AM 12/8/05 +0100, Ake Hedman, eurosource wrote:
> >This is the right approach surely. I'm at that state now and have no
> >other alternative then to back a bit and go through this "the right
> >way". I just have myself to blame. Have used watchdogs for many years on
> >PIC, AVR and other processors and expected no problem there except for
> >the usual forgetting to feed it in certain places. Oh well it's my first
> >project on this processor family so this makes me learn useful stuff
> >just as you write (just a bit hard to appreciate that right now ;-) ).
> >Really need the watchdog to work in this application though so there is
> >no shortcut.
>
> One thought that occurs to me, and I have no idea whether it is an issue
> with this processor, is that some watchdogs must be cleared before 
> they are
> enabled or you run the risk of them firing as soon as you enable
> them.  Whether or not they do depends on when you start them and how the
> registers initialize etc...
>
> Robert

Good thought! Sadly it did not help on my problems. But I agree this is 
probably something one should do. The watchdog is  initialized to 0xff 
on reset according to the manual. The question here is if it is updated 
while disabled or will stay at 0xff until enabled. Have to test that.

Thanks!
/Ake


>
> " 'Freedom' has no meaning of itself.  There are always 
> restrictions,   be
> they legal, genetic, or physical.  If you don't believe me, try to chew a
> radio signal. "  -- Kelvin Throop, III
> http://www.aeolusdevelopment.com/
>
>
>
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> <http://groups.yahoo.com/gads?t=ms&k=Pic+microcontrollers&w1=Microprocessor&w2=Microcontrollers&w3=Pic+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=TpkoX4KofDJ7c6LyBvUqVQ> 
>
> 8051 microprocessor 
> <http://groups.yahoo.com/gads?t=ms&k=8051+microprocessor&w1=Microprocessor&w2=Microcontrollers&w3=Pic+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=1Ipf1Fjfbd_HVIlekkDP-A> 
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-- 
 ---
Ake Hedman (YAP - Yet Another Programmer)
eurosource, Brattbergavägen 17, 820 50 LOS, Sweden
Phone: (46) 657 413430 Cellular: (46) 73 84 84 102
Company home: http://www.eurosource.se      
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Personal homepage: http://www.eurosource.se/akhe
Automated home: http://www.vscp.org



[Non-text portions of this message have been removed]

Re: Problem with watchdog

2005-12-09 by brendanmurphy37

Ken,

Can you explain why you think there's a problem with an interrupt 
between the two writes?

According to the User Manual: "Once 0xAA is written to
the WDFEED register the next operation in the Watchdog register space 
should be a WRITE (0x55) to the WDFFED register otherwise the 
watchdog is triggered."

I take this to mean that the next write to the WDFEED register has to 
be 0x55 following the 0xaa: why should it matter if this is one cycle 
on, or 1000 cycles on (e.g. to take account of any interrupt)? I'm 
assuming here that the interrupt itself doesn't go near the watchdog.

Also, for disabling interrupts, why not just disable IRQ and FIQ in 
the same write to the CPSR? Is there some problem with this?

regards
Brendan
 

--- In lpc2000@yahoogroups.com, "Ken Wada" <kwada@a...> wrote:
>
> Basically, your method works fine...
> UNTIL: you start adding interrupt service routines!
> 
> This is why:
> void WDOG_pet()
> {
> WDFEED = 0xAA;
> /*             Interrupt occurs here...> dog will NOT pet 
properly!!! 
> ***/
> WDFEED = 0x55;
> }
> 
> /**** example uses Keil compiler directives ***/
> /********** The following is what I wound up doing, (gotta avoid 
that 
> spurious interrupt issue with the ARM also!!! ***/
> 
> /**** The actual interface that everybody uses ***/
> void WDOG_pet (void)
> {
>     SYSSWI_service (12,0,0,0);
> }
> 
> /***** How the SYSSWI_service works, (based on SWI) ***/
> unsigned SYSSWI_service (SYSSWI opcode, int id, void *pObj, 
unsigned 
> _user1) __swi(12)
> {
>     switch (opcode)
>     {
>       case SYSSWI_WDOGPET:
>         SYSSWI_watchDogPet ();
>         break;
>       ...
>     }
>     return (0);
> }
> 
> /***** How the SYSSWI_watchDogPet () works ***/
> static void SYSSWI_watchDogPet (void)
> {
>     ARM_disableFIQ ();                /* make sure FIQ is 
disabled     
>      */
>     WDFEED  = 0xAA;
>     WDFEED  = 0x55;
>     ARM_enableFIQ ();                 /* re-enable the 
FIQ             
>      */
> }
> 
> /***** The IRQ is automatically disabled by vectoring to the SWI...
> however, you need to make the operation atomic with respect to FIQ, 
> which is NOT disabled ***/
> 
> PUBLIC  ARM_disableFIQ?A ; interface is ARM mode
> 
> ARM_disableFIQ?A  PROC  CODE32
>       MRS   R0,CPSR
>       ORR   R0,R0,#0x0040                   ; Mask just the FIQ
>       MSR   CPSR_c,R0
>       BX    R14
> 
>       ENDP
> 
> PUBLIC  ARM_enableFIQ?A ; interface is ARM mode
> 
> ARM_enableFIQ?A  PROC  CODE32
>       MRS   R0,CPSR
>       BIC   R0,R0,#0x0040                   ; Enable just the FIQ
>       MSR   CPSR_c,R0
>       BX    R14
> 
>       ENDP
> END
> 
> 
> --- In lpc2000@yahoogroups.com, "Ake Hedman, eurosource" 
<akhe@b...> 
> wrote:
> >
> > Hi all.
> > 
> > I am trying to enable the watchdog but the result is a total hang 
of 
> the 
> > board. Not even the bootloader is possible to reach after the 
crash 
> and 
> > I have to reapply power with P0.14 low to get access to the 
> botloader 
> > again. Reset is not enough.
> > 
> > The code to initialize the watchdog is
> > 
> >     // initialize the watchdog timer
> >     WDTC = 0xffffffff; // 15000000;                        // One 
> second 
> > = 15000000
> >     WDMOD = WDEN | WDRESET;                    // Activate 
watchdog
> >     WDFEED = 0xAA; WDFEED = 0x55;
> > 
> > I must have misunderstood the WD functionality. What am I doing 
> wrong? 
> > In the above code the watchdog should not trigger until 5 minutes 
> > elapsed so even if a vector should be wrong the code that follow 
> should 
> > run for a while but as soon as I write to the WDMOD register I 
get a 
Show quoted textHide quoted text
> hang.
> > 
> > /Ake
> > 
> > -- 
> >  ---
> > Ake Hedman (YAP - Yet Another Programmer)
> > eurosource, Brattbergavägen 17, 820 50 LOS, Sweden
> > Phone: (46) 657 413430 Cellular: (46) 73 84 84 102
> > Company home: http://www.eurosource.se      
> > Kryddor/Te/Kaffe: http://www.brattberg.com
> > Personal homepage: http://www.eurosource.se/akhe
> > Automated home: http://www.vscp.org
> >
>

Re: [lpc2000] Re: Problem with watchdog

2005-12-09 by Ake Hedman, eurosource

Ken,

yes this is probably it (as zdravko_k_d@... also pointed out 
earlier).  Strange not to have an atomic feed. First time I have come 
across that. I have the code taken apart now to try to track this down. 
But all the symptoms of the problems I have match what should be 
expected from the watchdog triggering from something else then not just 
lack of feed.

What happens if the watchdog is feed with the wrong sequence? Is it 
triggered or does it just ignore it?

Appreciate your input Ken.

/Ake

Ken Wada wrote:

> Basically, your method works fine...
> UNTIL: you start adding interrupt service routines!
>
> This is why:
> void WDOG_pet()
> {
> WDFEED = 0xAA;
> /*             Interrupt occurs here...> dog will NOT pet properly!!!
> ***/
> WDFEED = 0x55;
> }
>
> /**** example uses Keil compiler directives ***/
> /********** The following is what I wound up doing, (gotta avoid that
> spurious interrupt issue with the ARM also!!! ***/
>
> /**** The actual interface that everybody uses ***/
> void WDOG_pet (void)
> {
>     SYSSWI_service (12,0,0,0);
> }
>
> /***** How the SYSSWI_service works, (based on SWI) ***/
> unsigned SYSSWI_service (SYSSWI opcode, int id, void *pObj, unsigned
> _user1) __swi(12)
> {
>     switch (opcode)
>     {
>       case SYSSWI_WDOGPET:
>         SYSSWI_watchDogPet ();
>         break;
>       ...
>     }
>     return (0);
> }
>
> /***** How the SYSSWI_watchDogPet () works ***/
> static void SYSSWI_watchDogPet (void)
> {
>     ARM_disableFIQ ();                /* make sure FIQ is disabled    
>      */
>     WDFEED  = 0xAA;
>     WDFEED  = 0x55;
>     ARM_enableFIQ ();                 /* re-enable the FIQ            
>      */
> }
>
> /***** The IRQ is automatically disabled by vectoring to the SWI...
> however, you need to make the operation atomic with respect to FIQ,
> which is NOT disabled ***/
>
> PUBLIC  ARM_disableFIQ?A ; interface is ARM mode
>
> ARM_disableFIQ?A  PROC  CODE32
>       MRS   R0,CPSR
>       ORR   R0,R0,#0x0040                   ; Mask just the FIQ
>       MSR   CPSR_c,R0
>       BX    R14
>
>       ENDP
>
> PUBLIC  ARM_enableFIQ?A ; interface is ARM mode
>
> ARM_enableFIQ?A  PROC  CODE32
>       MRS   R0,CPSR
>       BIC   R0,R0,#0x0040                   ; Enable just the FIQ
>       MSR   CPSR_c,R0
>       BX    R14
>
>       ENDP
> END
>
>
> --- In lpc2000@yahoogroups.com, "Ake Hedman, eurosource" <akhe@b...>
> wrote:
> >
> > Hi all.
> >
> > I am trying to enable the watchdog but the result is a total hang of
> the
> > board. Not even the bootloader is possible to reach after the crash
> and
> > I have to reapply power with P0.14 low to get access to the
> botloader
> > again. Reset is not enough.
> >
> > The code to initialize the watchdog is
> >
> >     // initialize the watchdog timer
> >     WDTC = 0xffffffff; // 15000000;                        // One
> second
> > = 15000000
> >     WDMOD = WDEN | WDRESET;                    // Activate watchdog
> >     WDFEED = 0xAA; WDFEED = 0x55;
> >
> > I must have misunderstood the WD functionality. What am I doing
> wrong?
> > In the above code the watchdog should not trigger until 5 minutes
> > elapsed so even if a vector should be wrong the code that follow
> should
> > run for a while but as soon as I write to the WDMOD register I get a
> hang.
> >
> > /Ake
> >
> > --
> >  ---
> > Ake Hedman (YAP - Yet Another Programmer)
> > eurosource, Brattbergavägen 17, 820 50 LOS, Sweden
> > Phone: (46) 657 413430 Cellular: (46) 73 84 84 102
> > Company home: http://www.eurosource.se     
> > Kryddor/Te/Kaffe: http://www.brattberg.com
> > Personal homepage: http://www.eurosource.se/akhe
> > Automated home: http://www.vscp.org
> >
>
>
>
>
>
>
> SPONSORED LINKS
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> <http://groups.yahoo.com/gads?t=ms&k=Microprocessor&w1=Microprocessor&w2=Microcontrollers&w3=Pic+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=tsVC-J9hJ5qyXg0WPR0l6g> 
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> <http://groups.yahoo.com/gads?t=ms&k=Microcontrollers&w1=Microprocessor&w2=Microcontrollers&w3=Pic+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=DvJVNqC_pqRTm8Xq01nxwg> 
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>
>
>
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-- 
 ---
Ake Hedman (YAP - Yet Another Programmer)
eurosource, Brattbergavägen 17, 820 50 LOS, Sweden
Phone: (46) 657 413430 Cellular: (46) 73 84 84 102
Company home: http://www.eurosource.se      
Kryddor/Te/Kaffe: http://www.brattberg.com
Personal homepage: http://www.eurosource.se/akhe
Automated home: http://www.vscp.org



[Non-text portions of this message have been removed]

Re: Problem with watchdog

2005-12-09 by Ken Wada

From extensive testing...I have found that the LPC22xx just ignores an 
invalid feed.

I have come across this in Motorola's Power PC chip also.

Ken Wada

--- In lpc2000@yahoogroups.com, "Ake Hedman, eurosource" <akhe@b...> 
wrote:
>
> Ken,
> 
> yes this is probably it (as zdravko_k_d@y... also pointed out 
> earlier).  Strange not to have an atomic feed. First time I have 
come 
> across that. I have the code taken apart now to try to track this 
down. 
> But all the symptoms of the problems I have match what should be 
> expected from the watchdog triggering from something else then not 
just 
> lack of feed.
> 
> What happens if the watchdog is feed with the wrong sequence? Is it 
> triggered or does it just ignore it?
> 
> Appreciate your input Ken.
> 
> /Ake
> 
> Ken Wada wrote:
> 
> > Basically, your method works fine...
> > UNTIL: you start adding interrupt service routines!
> >
> > This is why:
> > void WDOG_pet()
> > {
> > WDFEED = 0xAA;
> > /*             Interrupt occurs here...> dog will NOT pet 
properly!!!
> > ***/
> > WDFEED = 0x55;
> > }
> >
> > /**** example uses Keil compiler directives ***/
> > /********** The following is what I wound up doing, (gotta avoid 
that
> > spurious interrupt issue with the ARM also!!! ***/
> >
> > /**** The actual interface that everybody uses ***/
> > void WDOG_pet (void)
> > {
> >     SYSSWI_service (12,0,0,0);
> > }
> >
> > /***** How the SYSSWI_service works, (based on SWI) ***/
> > unsigned SYSSWI_service (SYSSWI opcode, int id, void *pObj, 
unsigned
> > _user1) __swi(12)
> > {
> >     switch (opcode)
> >     {
> >       case SYSSWI_WDOGPET:
> >         SYSSWI_watchDogPet ();
> >         break;
> >       ...
> >     }
> >     return (0);
> > }
> >
> > /***** How the SYSSWI_watchDogPet () works ***/
> > static void SYSSWI_watchDogPet (void)
> > {
> >     ARM_disableFIQ ();                /* make sure FIQ is disabled 
   
> >      */
> >     WDFEED  = 0xAA;
> >     WDFEED  = 0x55;
> >     ARM_enableFIQ ();                 /* re-enable the FIQ         
   
> >      */
> > }
> >
> > /***** The IRQ is automatically disabled by vectoring to the SWI..
.
> > however, you need to make the operation atomic with respect to 
FIQ,
> > which is NOT disabled ***/
> >
> > PUBLIC  ARM_disableFIQ?A ; interface is ARM mode
> >
> > ARM_disableFIQ?A  PROC  CODE32
> >       MRS   R0,CPSR
> >       ORR   R0,R0,#0x0040                   ; Mask just the FIQ
> >       MSR   CPSR_c,R0
> >       BX    R14
> >
> >       ENDP
> >
> > PUBLIC  ARM_enableFIQ?A ; interface is ARM mode
> >
> > ARM_enableFIQ?A  PROC  CODE32
> >       MRS   R0,CPSR
> >       BIC   R0,R0,#0x0040                   ; Enable just the FIQ
> >       MSR   CPSR_c,R0
> >       BX    R14
> >
> >       ENDP
> > END
> >
> >
> > --- In lpc2000@yahoogroups.com, "Ake Hedman, eurosource" <akhe@b..
.>
> > wrote:
> > >
> > > Hi all.
> > >
> > > I am trying to enable the watchdog but the result is a total 
hang of
> > the
> > > board. Not even the bootloader is possible to reach after the 
crash
> > and
> > > I have to reapply power with P0.14 low to get access to the
> > botloader
> > > again. Reset is not enough.
> > >
> > > The code to initialize the watchdog is
> > >
> > >     // initialize the watchdog timer
> > >     WDTC = 0xffffffff; // 15000000;                        // 
One
> > second
> > > = 15000000
> > >     WDMOD = WDEN | WDRESET;                    // Activate 
watchdog
> > >     WDFEED = 0xAA; WDFEED = 0x55;
> > >
> > > I must have misunderstood the WD functionality. What am I doing
> > wrong?
> > > In the above code the watchdog should not trigger until 5 
minutes
> > > elapsed so even if a vector should be wrong the code that follow
> > should
> > > run for a while but as soon as I write to the WDMOD register I 
get a
> > hang.
> > >
> > > /Ake
> > >
> > > --
> > >  ---
> > > Ake Hedman (YAP - Yet Another Programmer)
> > > eurosource, Brattbergavägen 17, 820 50 LOS, Sweden
> > > Phone: (46) 657 413430 Cellular: (46) 73 84 84 102
> > > Company home: http://www.eurosource.se     
> > > Kryddor/Te/Kaffe: http://www.brattberg.com
> > > Personal homepage: http://www.eurosource.se/akhe
> > > Automated home: http://www.vscp.org
> > >
> >
> >
> >
> >
> >
> >
> > SPONSORED LINKS
> > Microprocessor 
> > <http://groups.yahoo.com/gads?
t=ms&k=Microprocessor&w1=Microprocessor&w2=Microcontrollers&w3=Pic+mic
rocontrollers&w4=8051+microprocessor&c=4&s=93&.
sig=tsVC-J9hJ5qyXg0WPR0l6g> 
> > 	Microcontrollers 
> > <http://groups.yahoo.com/gads?
t=ms&k=Microcontrollers&w1=Microprocessor&w2=Microcontrollers&w3=Pic+m
icrocontrollers&w4=8051+microprocessor&c=4&s=93&.
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> > 	Pic microcontrollers 
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t=ms&k=Pic+microcontrollers&w1=Microprocessor&w2=Microcontrollers&w3=P
ic+microcontrollers&w4=8051+microprocessor&c=4&s=93&.
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> >
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> > <http://groups.yahoo.com/gads?
t=ms&k=8051+microprocessor&w1=Microprocessor&w2=Microcontrollers&w3=Pi
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> >
> >
> >
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Show quoted textHide quoted text
> >
> 
> 
> -- 
>  ---
> Ake Hedman (YAP - Yet Another Programmer)
> eurosource, Brattbergavägen 17, 820 50 LOS, Sweden
> Phone: (46) 657 413430 Cellular: (46) 73 84 84 102
> Company home: http://www.eurosource.se      
> Kryddor/Te/Kaffe: http://www.brattberg.com
> Personal homepage: http://www.eurosource.se/akhe
> Automated home: http://www.vscp.org
> 
> 
> 
> [Non-text portions of this message have been removed]
>

Re: Problem with watchdog

2005-12-09 by Ken Wada

--- In lpc2000@yahoogroups.com, "brendanmurphy37" <brendan.murphy@i...
> wrote:
>
> 
> Ken,
> 
> Can you explain why you think there's a problem with an interrupt 
> between the two writes?
> 
> According to the User Manual: "Once 0xAA is written to
> the WDFEED register the next operation in the Watchdog register 
space 
> should be a WRITE (0x55) to the WDFFED register otherwise the 
> watchdog is triggered."
> 
> I take this to mean that the next write to the WDFEED register has 
to 
> be 0x55 following the 0xaa: why should it matter if this is one 
cycle 
> on, or 1000 cycles on (e.g. to take account of any interrupt)? I'm 
> assuming here that the interrupt itself doesn't go near the 
watchdog.
It makes a bit difference! If you WRITE (0x55), the processor expects 
a WRITE(0xAA) on  the very next cycle. If this is done outside an 
interrupt context, the interrupt service routine will pretty much 
guarantee that this condition is violated!

> 
> Also, for disabling interrupts, why not just disable IRQ and FIQ in 
> the same write to the CPSR? Is there some problem with this?
Yep...huge problem. Actually, you will see this type of problem with 
many processors/especially DSP's with fully pipelined architecture. 
The Philips User manual calls this the spurious interrupt problem. 
Actually, Philips basically took their cautionary note directly from 
the ARM users guide.

Gone are the good-old days of doing something like EA=0, as per 8051..
.these pipelined architectures are a bit different when it comes to 
instruction processing.

Fortunately, all of these modern architectures give you a way to do 
these types of operations, (albeit with a bit more effort), via some 
software interrupt (SWI) instruction.

My 1st encounter with this was with the Intel 80386 chip. This chip 
had an instruction pipeline, and I had to use the int86() SWI command 
in order to properly code up the atomic sections.

Ken Wada
> 
> regards
> Brendan
>  
> 
> --- In lpc2000@yahoogroups.com, "Ken Wada" <kwada@a...> wrote:
> >
> > Basically, your method works fine...
> > UNTIL: you start adding interrupt service routines!
> > 
> > This is why:
> > void WDOG_pet()
> > {
> > WDFEED = 0xAA;
> > /*             Interrupt occurs here...> dog will NOT pet 
> properly!!! 
> > ***/
> > WDFEED = 0x55;
> > }
> > 
> > /**** example uses Keil compiler directives ***/
> > /********** The following is what I wound up doing, (gotta avoid 
> that 
> > spurious interrupt issue with the ARM also!!! ***/
> > 
> > /**** The actual interface that everybody uses ***/
> > void WDOG_pet (void)
> > {
> >     SYSSWI_service (12,0,0,0);
> > }
> > 
> > /***** How the SYSSWI_service works, (based on SWI) ***/
> > unsigned SYSSWI_service (SYSSWI opcode, int id, void *pObj, 
> unsigned 
> > _user1) __swi(12)
> > {
> >     switch (opcode)
> >     {
> >       case SYSSWI_WDOGPET:
> >         SYSSWI_watchDogPet ();
> >         break;
> >       ...
> >     }
> >     return (0);
> > }
> > 
> > /***** How the SYSSWI_watchDogPet () works ***/
> > static void SYSSWI_watchDogPet (void)
> > {
> >     ARM_disableFIQ ();                /* make sure FIQ is 
> disabled     
> >      */
> >     WDFEED  = 0xAA;
> >     WDFEED  = 0x55;
> >     ARM_enableFIQ ();                 /* re-enable the 
> FIQ             
> >      */
> > }
> > 
> > /***** The IRQ is automatically disabled by vectoring to the SWI..
.
> > however, you need to make the operation atomic with respect to 
FIQ, 
> > which is NOT disabled ***/
> > 
> > PUBLIC  ARM_disableFIQ?A ; interface is ARM mode
> > 
> > ARM_disableFIQ?A  PROC  CODE32
> >       MRS   R0,CPSR
> >       ORR   R0,R0,#0x0040                   ; Mask just the FIQ
> >       MSR   CPSR_c,R0
> >       BX    R14
> > 
> >       ENDP
> > 
> > PUBLIC  ARM_enableFIQ?A ; interface is ARM mode
> > 
> > ARM_enableFIQ?A  PROC  CODE32
> >       MRS   R0,CPSR
> >       BIC   R0,R0,#0x0040                   ; Enable just the FIQ
> >       MSR   CPSR_c,R0
> >       BX    R14
> > 
> >       ENDP
> > END
> > 
> > 
> > --- In lpc2000@yahoogroups.com, "Ake Hedman, eurosource" 
> <akhe@b...> 
> > wrote:
> > >
> > > Hi all.
> > > 
> > > I am trying to enable the watchdog but the result is a total 
hang 
> of 
> > the 
> > > board. Not even the bootloader is possible to reach after the 
> crash 
> > and 
> > > I have to reapply power with P0.14 low to get access to the 
> > botloader 
> > > again. Reset is not enough.
> > > 
> > > The code to initialize the watchdog is
> > > 
> > >     // initialize the watchdog timer
> > >     WDTC = 0xffffffff; // 15000000;                        // 
One 
> > second 
> > > = 15000000
> > >     WDMOD = WDEN | WDRESET;                    // Activate 
> watchdog
> > >     WDFEED = 0xAA; WDFEED = 0x55;
> > > 
> > > I must have misunderstood the WD functionality. What am I doing 
> > wrong? 
> > > In the above code the watchdog should not trigger until 5 
minutes 
Show quoted textHide quoted text
> > > elapsed so even if a vector should be wrong the code that follow 
> > should 
> > > run for a while but as soon as I write to the WDMOD register I 
> get a 
> > hang.
> > > 
> > > /Ake
> > > 
> > > -- 
> > >  ---
> > > Ake Hedman (YAP - Yet Another Programmer)
> > > eurosource, Brattbergavägen 17, 820 50 LOS, Sweden
> > > Phone: (46) 657 413430 Cellular: (46) 73 84 84 102
> > > Company home: http://www.eurosource.se      
> > > Kryddor/Te/Kaffe: http://www.brattberg.com
> > > Personal homepage: http://www.eurosource.se/akhe
> > > Automated home: http://www.vscp.org
> > >
> >
>

Re: [lpc2000] Re: Problem with watchdog

2005-12-09 by David Hawkins

Hi guys,

The uCOS-II RTOS port for the ARM processor defines an
OS_ENTER_CRITICAL and OS_EXIT_CRITICAL pair of macros,
inside which you can perform atomic (well, non-interruptible
operations). These aren't just limited to the RTOS
though.

The code snippet below is based on:

http://www.atmel.com/dyn/resources/prod_documents/DOC1156.PDF

Perhaps you want to add something like this to
protect your watchdog code.

Dave



from the UCOS-II os_cpu.h header:

#define  OS_ENTER_CRITICAL()  {cpu_sr = OS_CPU_SR_Save();}
#define  OS_EXIT_CRITICAL()   {OS_CPU_SR_Restore(cpu_sr);}

from the UCOS-II os_cpu_a.asm code:

@*********************************************************************************************************
@                                   CRITICAL SECTION METHOD 3 FUNCTION
@
@ Description: Disable/Enable interrupts by preserving the state of 
interrupts.  Generally speaking you
@              would store the state of the interrupt disable flag in 
the local variable 'cpu_sr' and then
@              disable interrupts.  'cpu_sr' is allocated in all of 
uC/OS-II's functions that need to
@              disable interrupts.  You would restore the interrupt 
disable state by copying back 'cpu_sr'
@              into the CPU's status register.
@
@ Prototypes :     OS_CPU_SR  OS_CPU_SR_Save(void);
@                  void       OS_CPU_SR_Restore(OS_CPU_SR cpu_sr);
@
@
@ Note(s)    : 1) These functions are used in general like this:
@
@                 void Task (void *p_arg)
@                 {
@                 #if OS_CRITICAL_METHOD == 3          /* Allocate 
storage for CPU status register */
@                     OS_CPU_SR  cpu_sr;
@                 #endif
@
@                          :
@                          :
@                     OS_ENTER_CRITICAL();             /* cpu_sr = 
OS_CPU_SaveSR();                */
@                          :
@                          :
@                     OS_EXIT_CRITICAL();              /* 
OS_CPU_RestoreSR(cpu_sr);                */
@                          :
@                          :
@                 }
@
@              2) OS_CPU_SR_Save() is implemented as recommended by 
Atmel's application note:
@
@                    "Disabling Interrupts at Processor Level"
@
@                 p328 of the ARM System Developers Guide has the first 
three asm statements and
@                 does not use the check.
@
@                 NOTE: the flags can ONLY be modified by a priviledged 
mode, so if you accidentally
@                 call this function from user-mode, the processor will 
lock up (in the loop check).
@
@*********************************************************************************************************

         .text
         .arm
	.align	2
	.func	OS_CPU_SR_Save

OS_CPU_SR_Save:
         MRS     R0,CPSR                     @ Set IRQ and FIQ bits in 
CPSR to disable all interrupts
         ORR     R1,R0,#I_Bit|F_Bit
         MSR     CPSR_c,R1

         @ Interrupt disable check:
         @
         @ This is a slight variation on the Atmel app note code,
         @ as it checks that both FIQ and IRQ disable bits get set.

         MRS     R1,CPSR                     @ Confirm that CPSR 
contains the proper interrupt disable flags
         AND     R1,R1,#I_Bit|F_Bit
         CMP     R1,#I_Bit|F_Bit
         BNE     OS_CPU_SR_Save              @ Not properly disabled 
(try again)

         MOV     PC,LR                       @ Disabled, return the 
original CPSR contents in R0
	.endfunc

         .text
         .arm
	.align	2
	.func	OS_CPU_SR_Restore

OS_CPU_SR_Restore:
         MSR     CPSR_c,R0
         MOV     PC,LR
	.endfunc

Re: Problem with watchdog

2005-12-09 by brendanmurphy37

Ken,

I'm still curous about your statement "the processor expects
a WRITE(0xAA) on the very next cycle". Where is this documented? It 
may be true, but if so, I'd say it contradicts the quote I took from 
the User Manual (for the LPC213x parts). Or am I misreading what it 
says?

It's a fairly important point: if the feed has to be done in two 
adjacent CPU cycles, you're forced to use assembler apart from 
anything else, in order to do the back-to-back write reliably (I've 
checked the assembler o/p from our own code, and it does, but you 
can't rely on this: all you need is to change the revision of the 
compiler or have a new optimsaition setting and thinmgs can fall 
apart).

On the other point: you're quite right - there's plenty of "gotchas" 
with ARM interrupts. It's been a while since I looked at this, but I 
seem to recall spending at least a few days armed with a stack of 
ARM books/manuals etc. (if you'll forgive the pun) to get our 
interrupt handling code to a state we were happy with it. Funny how 
you forget such things... I think what prompted my question was the 
implication that you somehow couldn't set both bits at the same 
time. As the other response on this points out, you can of course, 
and it works, but maybe not in quite the way you'd expect.....

I'd apreciate an answer on the watchdog issue though, as it's very 
much a live issue with us at the moment.

Regards
Brendan


--- In lpc2000@yahoogroups.com, "Ken Wada" <kwada@a...> wrote:
>
> --- In lpc2000@yahoogroups.com, "brendanmurphy37" 
<brendan.murphy@i...
> > wrote:
> >
> > 
> > Ken,
> > 
> > Can you explain why you think there's a problem with an 
interrupt 
> > between the two writes?
> > 
> > According to the User Manual: "Once 0xAA is written to
> > the WDFEED register the next operation in the Watchdog register 
> space 
> > should be a WRITE (0x55) to the WDFFED register otherwise the 
> > watchdog is triggered."
> > 
> > I take this to mean that the next write to the WDFEED register 
has 
> to 
> > be 0x55 following the 0xaa: why should it matter if this is one 
> cycle 
> > on, or 1000 cycles on (e.g. to take account of any interrupt)? 
I'm 
> > assuming here that the interrupt itself doesn't go near the 
> watchdog.
> It makes a bit difference! If you WRITE (0x55), the processor 
expects 
> a WRITE(0xAA) on  the very next cycle. If this is done outside an 
> interrupt context, the interrupt service routine will pretty much 
> guarantee that this condition is violated!
> 
> > 
> > Also, for disabling interrupts, why not just disable IRQ and FIQ 
in 
> > the same write to the CPSR? Is there some problem with this?
> Yep...huge problem. Actually, you will see this type of problem 
with 
> many processors/especially DSP's with fully pipelined 
architecture. 
> The Philips User manual calls this the spurious interrupt problem. 
> Actually, Philips basically took their cautionary note directly 
from 
> the ARM users guide.
> 
> Gone are the good-old days of doing something like EA=0, as per 
8051..
> .these pipelined architectures are a bit different when it comes 
to 
> instruction processing.
> 
> Fortunately, all of these modern architectures give you a way to 
do 
> these types of operations, (albeit with a bit more effort), via 
some 
> software interrupt (SWI) instruction.
> 
> My 1st encounter with this was with the Intel 80386 chip. This 
chip 
> had an instruction pipeline, and I had to use the int86() SWI 
command 
> in order to properly code up the atomic sections.
> 
> Ken Wada
> > 
> > regards
> > Brendan
> >  
> > 
> > --- In lpc2000@yahoogroups.com, "Ken Wada" <kwada@a...> wrote:
> > >
> > > Basically, your method works fine...
> > > UNTIL: you start adding interrupt service routines!
> > > 
> > > This is why:
> > > void WDOG_pet()
> > > {
> > > WDFEED = 0xAA;
> > > /*             Interrupt occurs here...> dog will NOT pet 
> > properly!!! 
> > > ***/
> > > WDFEED = 0x55;
> > > }
> > > 
> > > /**** example uses Keil compiler directives ***/
> > > /********** The following is what I wound up doing, (gotta 
avoid 
> > that 
> > > spurious interrupt issue with the ARM also!!! ***/
> > > 
> > > /**** The actual interface that everybody uses ***/
> > > void WDOG_pet (void)
> > > {
> > >     SYSSWI_service (12,0,0,0);
> > > }
> > > 
> > > /***** How the SYSSWI_service works, (based on SWI) ***/
> > > unsigned SYSSWI_service (SYSSWI opcode, int id, void *pObj, 
> > unsigned 
> > > _user1) __swi(12)
> > > {
> > >     switch (opcode)
> > >     {
> > >       case SYSSWI_WDOGPET:
> > >         SYSSWI_watchDogPet ();
> > >         break;
> > >       ...
> > >     }
> > >     return (0);
> > > }
> > > 
> > > /***** How the SYSSWI_watchDogPet () works ***/
> > > static void SYSSWI_watchDogPet (void)
> > > {
> > >     ARM_disableFIQ ();                /* make sure FIQ is 
> > disabled     
> > >      */
> > >     WDFEED  = 0xAA;
> > >     WDFEED  = 0x55;
> > >     ARM_enableFIQ ();                 /* re-enable the 
> > FIQ             
> > >      */
> > > }
> > > 
> > > /***** The IRQ is automatically disabled by vectoring to the 
SWI..
> .
> > > however, you need to make the operation atomic with respect to 
> FIQ, 
> > > which is NOT disabled ***/
> > > 
> > > PUBLIC  ARM_disableFIQ?A ; interface is ARM mode
> > > 
> > > ARM_disableFIQ?A  PROC  CODE32
> > >       MRS   R0,CPSR
> > >       ORR   R0,R0,#0x0040                   ; Mask just the FIQ
> > >       MSR   CPSR_c,R0
> > >       BX    R14
> > > 
> > >       ENDP
> > > 
> > > PUBLIC  ARM_enableFIQ?A ; interface is ARM mode
> > > 
> > > ARM_enableFIQ?A  PROC  CODE32
> > >       MRS   R0,CPSR
> > >       BIC   R0,R0,#0x0040                   ; Enable just the 
FIQ
> > >       MSR   CPSR_c,R0
> > >       BX    R14
> > > 
> > >       ENDP
> > > END
> > > 
> > > 
> > > --- In lpc2000@yahoogroups.com, "Ake Hedman, eurosource" 
> > <akhe@b...> 
> > > wrote:
> > > >
> > > > Hi all.
> > > > 
> > > > I am trying to enable the watchdog but the result is a total 
> hang 
> > of 
> > > the 
> > > > board. Not even the bootloader is possible to reach after 
the 
> > crash 
> > > and 
> > > > I have to reapply power with P0.14 low to get access to the 
> > > botloader 
> > > > again. Reset is not enough.
> > > > 
> > > > The code to initialize the watchdog is
> > > > 
> > > >     // initialize the watchdog timer
> > > >     WDTC = 0xffffffff; // 
15000000;                        // 
> One 
> > > second 
> > > > = 15000000
> > > >     WDMOD = WDEN | WDRESET;                    // Activate 
> > watchdog
> > > >     WDFEED = 0xAA; WDFEED = 0x55;
> > > > 
> > > > I must have misunderstood the WD functionality. What am I 
doing 
> > > wrong? 
> > > > In the above code the watchdog should not trigger until 5 
> minutes 
> > > > elapsed so even if a vector should be wrong the code that 
follow 
> > > should 
> > > > run for a while but as soon as I write to the WDMOD register 
I 
Show quoted textHide quoted text
> > get a 
> > > hang.
> > > > 
> > > > /Ake
> > > > 
> > > > -- 
> > > >  ---
> > > > Ake Hedman (YAP - Yet Another Programmer)
> > > > eurosource, Brattbergavägen 17, 820 50 LOS, Sweden
> > > > Phone: (46) 657 413430 Cellular: (46) 73 84 84 102
> > > > Company home: http://www.eurosource.se      
> > > > Kryddor/Te/Kaffe: http://www.brattberg.com
> > > > Personal homepage: http://www.eurosource.se/akhe
> > > > Automated home: http://www.vscp.org
> > > >
> > >
> >
>

Re: Problem with watchdog

2005-12-09 by brendanmurphy37

Ken,

If you follow workaround 1 in the ATMEL app note (and some of the 
examples in some of the ARM documentation) referred to in the other 
response to this, you can simplify greatly the code for what you're 
trying to achieve in relation to locking out both IRQ and FIQ 
interrupts.

As I mentioned in my previous response to this, we spent a lot of 
time looking into this whole area. We ended up writing our own IRQ 
pre-amble and post-amble code to ensure we had the correct 
environment i.e. no modification of the SPSR, interrupts disabled 
for the minimum length of time, ability to call standard 'C' 
function as the main body of the interrupt handler (i.e. no need for 
special __interrupt modifier of any kind etc. etc.)

I say "writing our own", but it was pretty much a copy of an ARM 
example, which we modified to load the 'C' handler from the VIC. I 
don't have the particular document to hand, but it's available from 
the ARM Web site.

As you say, it was all a lot easier in the 8-bit world, but given 
the choice, I know which I'd take....

Brendan

--- In lpc2000@yahoogroups.com, "Ken Wada" <kwada@a...> wrote:
>
> --- In lpc2000@yahoogroups.com, "brendanmurphy37" 
<brendan.murphy@i...
> > wrote:
> >
> > 
> > Ken,
> > 
> > Can you explain why you think there's a problem with an 
interrupt 
> > between the two writes?
> > 
> > According to the User Manual: "Once 0xAA is written to
> > the WDFEED register the next operation in the Watchdog register 
> space 
> > should be a WRITE (0x55) to the WDFFED register otherwise the 
> > watchdog is triggered."
> > 
> > I take this to mean that the next write to the WDFEED register 
has 
> to 
> > be 0x55 following the 0xaa: why should it matter if this is one 
> cycle 
> > on, or 1000 cycles on (e.g. to take account of any interrupt)? 
I'm 
> > assuming here that the interrupt itself doesn't go near the 
> watchdog.
> It makes a bit difference! If you WRITE (0x55), the processor 
expects 
> a WRITE(0xAA) on  the very next cycle. If this is done outside an 
> interrupt context, the interrupt service routine will pretty much 
> guarantee that this condition is violated!
> 
> > 
> > Also, for disabling interrupts, why not just disable IRQ and FIQ 
in 
> > the same write to the CPSR? Is there some problem with this?
> Yep...huge problem. Actually, you will see this type of problem 
with 
> many processors/especially DSP's with fully pipelined 
architecture. 
> The Philips User manual calls this the spurious interrupt problem. 
> Actually, Philips basically took their cautionary note directly 
from 
> the ARM users guide.
> 
> Gone are the good-old days of doing something like EA=0, as per 
8051..
> .these pipelined architectures are a bit different when it comes 
to 
> instruction processing.
> 
> Fortunately, all of these modern architectures give you a way to 
do 
> these types of operations, (albeit with a bit more effort), via 
some 
> software interrupt (SWI) instruction.
> 
> My 1st encounter with this was with the Intel 80386 chip. This 
chip 
> had an instruction pipeline, and I had to use the int86() SWI 
command 
> in order to properly code up the atomic sections.
> 
> Ken Wada
> > 
> > regards
> > Brendan
> >  
> > 
> > --- In lpc2000@yahoogroups.com, "Ken Wada" <kwada@a...> wrote:
> > >
> > > Basically, your method works fine...
> > > UNTIL: you start adding interrupt service routines!
> > > 
> > > This is why:
> > > void WDOG_pet()
> > > {
> > > WDFEED = 0xAA;
> > > /*             Interrupt occurs here...> dog will NOT pet 
> > properly!!! 
> > > ***/
> > > WDFEED = 0x55;
> > > }
> > > 
> > > /**** example uses Keil compiler directives ***/
> > > /********** The following is what I wound up doing, (gotta 
avoid 
> > that 
> > > spurious interrupt issue with the ARM also!!! ***/
> > > 
> > > /**** The actual interface that everybody uses ***/
> > > void WDOG_pet (void)
> > > {
> > >     SYSSWI_service (12,0,0,0);
> > > }
> > > 
> > > /***** How the SYSSWI_service works, (based on SWI) ***/
> > > unsigned SYSSWI_service (SYSSWI opcode, int id, void *pObj, 
> > unsigned 
> > > _user1) __swi(12)
> > > {
> > >     switch (opcode)
> > >     {
> > >       case SYSSWI_WDOGPET:
> > >         SYSSWI_watchDogPet ();
> > >         break;
> > >       ...
> > >     }
> > >     return (0);
> > > }
> > > 
> > > /***** How the SYSSWI_watchDogPet () works ***/
> > > static void SYSSWI_watchDogPet (void)
> > > {
> > >     ARM_disableFIQ ();                /* make sure FIQ is 
> > disabled     
> > >      */
> > >     WDFEED  = 0xAA;
> > >     WDFEED  = 0x55;
> > >     ARM_enableFIQ ();                 /* re-enable the 
> > FIQ             
> > >      */
> > > }
> > > 
> > > /***** The IRQ is automatically disabled by vectoring to the 
SWI..
> .
> > > however, you need to make the operation atomic with respect to 
> FIQ, 
> > > which is NOT disabled ***/
> > > 
> > > PUBLIC  ARM_disableFIQ?A ; interface is ARM mode
> > > 
> > > ARM_disableFIQ?A  PROC  CODE32
> > >       MRS   R0,CPSR
> > >       ORR   R0,R0,#0x0040                   ; Mask just the FIQ
> > >       MSR   CPSR_c,R0
> > >       BX    R14
> > > 
> > >       ENDP
> > > 
> > > PUBLIC  ARM_enableFIQ?A ; interface is ARM mode
> > > 
> > > ARM_enableFIQ?A  PROC  CODE32
> > >       MRS   R0,CPSR
> > >       BIC   R0,R0,#0x0040                   ; Enable just the 
FIQ
> > >       MSR   CPSR_c,R0
> > >       BX    R14
> > > 
> > >       ENDP
> > > END
> > > 
> > > 
> > > --- In lpc2000@yahoogroups.com, "Ake Hedman, eurosource" 
> > <akhe@b...> 
> > > wrote:
> > > >
> > > > Hi all.
> > > > 
> > > > I am trying to enable the watchdog but the result is a total 
> hang 
> > of 
> > > the 
> > > > board. Not even the bootloader is possible to reach after 
the 
> > crash 
> > > and 
> > > > I have to reapply power with P0.14 low to get access to the 
> > > botloader 
> > > > again. Reset is not enough.
> > > > 
> > > > The code to initialize the watchdog is
> > > > 
> > > >     // initialize the watchdog timer
> > > >     WDTC = 0xffffffff; // 
15000000;                        // 
> One 
> > > second 
> > > > = 15000000
> > > >     WDMOD = WDEN | WDRESET;                    // Activate 
> > watchdog
> > > >     WDFEED = 0xAA; WDFEED = 0x55;
> > > > 
> > > > I must have misunderstood the WD functionality. What am I 
doing 
> > > wrong? 
> > > > In the above code the watchdog should not trigger until 5 
> minutes 
> > > > elapsed so even if a vector should be wrong the code that 
follow 
> > > should 
> > > > run for a while but as soon as I write to the WDMOD register 
I 
Show quoted textHide quoted text
> > get a 
> > > hang.
> > > > 
> > > > /Ake
> > > > 
> > > > -- 
> > > >  ---
> > > > Ake Hedman (YAP - Yet Another Programmer)
> > > > eurosource, Brattbergavägen 17, 820 50 LOS, Sweden
> > > > Phone: (46) 657 413430 Cellular: (46) 73 84 84 102
> > > > Company home: http://www.eurosource.se      
> > > > Kryddor/Te/Kaffe: http://www.brattberg.com
> > > > Personal homepage: http://www.eurosource.se/akhe
> > > > Automated home: http://www.vscp.org
> > > >
> > >
> >
>

Re: Problem with watchdog

2005-12-09 by Ken Wada

Asynchronously turning off and on interrupts in the main body of your 
code is problematic. Instead of tempting fate; I decided to play the 
overly-cautious role. It is the following excerpt from the Philips 
User Manual that gave me pause:

"Although the example shows both IRQ and FIQ interrupts being 
disabled, similar behavior occurs when only one of the two
interrupt types is being disabled. The fact that the core processes 
the IRQ after completion of the MSR instruction which disables
IRQs does not normally cause a problem, since an interrupt arriving 
just one cycle earlier would be expected to be taken. When
the interrupt routine returns with an instruction like:
SUBS pc, lr, #4
the SPSR_IRQ is restored to the CPSR. The CPSR will now have the I bit 
and F bit set, and therefore execution will continue
with all interrupts disabled."

So....instead of taking the 'easy way' I decided to create a system 
where I had a reasonable, (probably overkill), that the system would 
work under all circumstances.

I really hate debugging spurious stuff. I have done this too many 
times on those fully pipelined DSP architectures...and did not want to 
tempt it this time with the ARM7TDMI.

I am sure, that over time, doing the simple turning interrupts on and 
off at will may work, with little detrimental effect...however, from 
what I read in the ARM website, and the Philips User Manual...

Let us say, I am pretty sure that the methods I proposed...albeit a 
bit more long-winded and non-trivial; are assured to work in all 
cases.

So far; I have not been called in on any suspected crashes, system 
glitches, and intermittent Watchdogs...and this on equipment that is 
operating 24x7 with full status monitoring for DOG events.

Ken Wada


--- In lpc2000@yahoogroups.com, "brendanmurphy37" <brendan.murphy@i...
> wrote:
>
> 
> Ken,
> 
> If you follow workaround 1 in the ATMEL app note (and some of the 
> examples in some of the ARM documentation) referred to in the other 
> response to this, you can simplify greatly the code for what you're 
> trying to achieve in relation to locking out both IRQ and FIQ 
> interrupts.
> 
> As I mentioned in my previous response to this, we spent a lot of 
> time looking into this whole area. We ended up writing our own IRQ 
> pre-amble and post-amble code to ensure we had the correct 
> environment i.e. no modification of the SPSR, interrupts disabled 
> for the minimum length of time, ability to call standard 'C' 
> function as the main body of the interrupt handler (i.e. no need for 
> special __interrupt modifier of any kind etc. etc.)
> 
> I say "writing our own", but it was pretty much a copy of an ARM 
> example, which we modified to load the 'C' handler from the VIC. I 
> don't have the particular document to hand, but it's available from 
> the ARM Web site.
> 
> As you say, it was all a lot easier in the 8-bit world, but given 
> the choice, I know which I'd take....
> 
> Brendan
> 
> --- In lpc2000@yahoogroups.com, "Ken Wada" <kwada@a...> wrote:
> >
> > --- In lpc2000@yahoogroups.com, "brendanmurphy37" 
> <brendan.murphy@i...
> > > wrote:
> > >
> > > 
> > > Ken,
> > > 
> > > Can you explain why you think there's a problem with an 
> interrupt 
> > > between the two writes?
> > > 
> > > According to the User Manual: "Once 0xAA is written to
> > > the WDFEED register the next operation in the Watchdog register 
> > space 
> > > should be a WRITE (0x55) to the WDFFED register otherwise the 
> > > watchdog is triggered."
> > > 
> > > I take this to mean that the next write to the WDFEED register 
> has 
> > to 
> > > be 0x55 following the 0xaa: why should it matter if this is one 
> > cycle 
> > > on, or 1000 cycles on (e.g. to take account of any interrupt)? 
> I'm 
> > > assuming here that the interrupt itself doesn't go near the 
> > watchdog.
> > It makes a bit difference! If you WRITE (0x55), the processor 
> expects 
> > a WRITE(0xAA) on  the very next cycle. If this is done outside an 
> > interrupt context, the interrupt service routine will pretty much 
> > guarantee that this condition is violated!
> > 
> > > 
> > > Also, for disabling interrupts, why not just disable IRQ and FIQ 
> in 
> > > the same write to the CPSR? Is there some problem with this?
> > Yep...huge problem. Actually, you will see this type of problem 
> with 
> > many processors/especially DSP's with fully pipelined 
> architecture. 
> > The Philips User manual calls this the spurious interrupt problem. 
> > Actually, Philips basically took their cautionary note directly 
> from 
> > the ARM users guide.
> > 
> > Gone are the good-old days of doing something like EA=0, as per 
> 8051..
> > .these pipelined architectures are a bit different when it comes 
> to 
> > instruction processing.
> > 
> > Fortunately, all of these modern architectures give you a way to 
> do 
> > these types of operations, (albeit with a bit more effort), via 
> some 
> > software interrupt (SWI) instruction.
> > 
> > My 1st encounter with this was with the Intel 80386 chip. This 
> chip 
> > had an instruction pipeline, and I had to use the int86() SWI 
> command 
> > in order to properly code up the atomic sections.
> > 
> > Ken Wada
> > > 
> > > regards
> > > Brendan
> > >  
> > > 
> > > --- In lpc2000@yahoogroups.com, "Ken Wada" <kwada@a...> wrote:
> > > >
> > > > Basically, your method works fine...
> > > > UNTIL: you start adding interrupt service routines!
> > > > 
> > > > This is why:
> > > > void WDOG_pet()
> > > > {
> > > > WDFEED = 0xAA;
> > > > /*             Interrupt occurs here...> dog will NOT pet 
> > > properly!!! 
> > > > ***/
> > > > WDFEED = 0x55;
> > > > }
> > > > 
> > > > /**** example uses Keil compiler directives ***/
> > > > /********** The following is what I wound up doing, (gotta 
> avoid 
> > > that 
> > > > spurious interrupt issue with the ARM also!!! ***/
> > > > 
> > > > /**** The actual interface that everybody uses ***/
> > > > void WDOG_pet (void)
> > > > {
> > > >     SYSSWI_service (12,0,0,0);
> > > > }
> > > > 
> > > > /***** How the SYSSWI_service works, (based on SWI) ***/
> > > > unsigned SYSSWI_service (SYSSWI opcode, int id, void *pObj, 
> > > unsigned 
> > > > _user1) __swi(12)
> > > > {
> > > >     switch (opcode)
> > > >     {
> > > >       case SYSSWI_WDOGPET:
> > > >         SYSSWI_watchDogPet ();
> > > >         break;
> > > >       ...
> > > >     }
> > > >     return (0);
> > > > }
> > > > 
> > > > /***** How the SYSSWI_watchDogPet () works ***/
> > > > static void SYSSWI_watchDogPet (void)
> > > > {
> > > >     ARM_disableFIQ ();                /* make sure FIQ is 
> > > disabled     
> > > >      */
> > > >     WDFEED  = 0xAA;
> > > >     WDFEED  = 0x55;
> > > >     ARM_enableFIQ ();                 /* re-enable the 
> > > FIQ             
> > > >      */
> > > > }
> > > > 
> > > > /***** The IRQ is automatically disabled by vectoring to the 
> SWI..
> > .
> > > > however, you need to make the operation atomic with respect to 
> > FIQ, 
> > > > which is NOT disabled ***/
> > > > 
> > > > PUBLIC  ARM_disableFIQ?A ; interface is ARM mode
> > > > 
> > > > ARM_disableFIQ?A  PROC  CODE32
> > > >       MRS   R0,CPSR
> > > >       ORR   R0,R0,#0x0040                   ; Mask just the 
FIQ
Show quoted textHide quoted text
> > > >       MSR   CPSR_c,R0
> > > >       BX    R14
> > > > 
> > > >       ENDP
> > > > 
> > > > PUBLIC  ARM_enableFIQ?A ; interface is ARM mode
> > > > 
> > > > ARM_enableFIQ?A  PROC  CODE32
> > > >       MRS   R0,CPSR
> > > >       BIC   R0,R0,#0x0040                   ; Enable just the 
> FIQ
> > > >       MSR   CPSR_c,R0
> > > >       BX    R14
> > > > 
> > > >       ENDP
> > > > END
> > > > 
> > > > 
> > > > --- In lpc2000@yahoogroups.com, "Ake Hedman, eurosource" 
> > > <akhe@b...> 
> > > > wrote:
> > > > >
> > > > > Hi all.
> > > > > 
> > > > > I am trying to enable the watchdog but the result is a total 
> > hang 
> > > of 
> > > > the 
> > > > > board. Not even the bootloader is possible to reach after 
> the 
> > > crash 
> > > > and 
> > > > > I have to reapply power with P0.14 low to get access to the 
> > > > botloader 
> > > > > again. Reset is not enough.
> > > > > 
> > > > > The code to initialize the watchdog is
> > > > > 
> > > > >     // initialize the watchdog timer
> > > > >     WDTC = 0xffffffff; // 
> 15000000;                        // 
> > One 
> > > > second 
> > > > > = 15000000
> > > > >     WDMOD = WDEN | WDRESET;                    // Activate 
> > > watchdog
> > > > >     WDFEED = 0xAA; WDFEED = 0x55;
> > > > > 
> > > > > I must have misunderstood the WD functionality. What am I 
> doing 
> > > > wrong? 
> > > > > In the above code the watchdog should not trigger until 5 
> > minutes 
> > > > > elapsed so even if a vector should be wrong the code that 
> follow 
> > > > should 
> > > > > run for a while but as soon as I write to the WDMOD register 
> I 
> > > get a 
> > > > hang.
> > > > > 
> > > > > /Ake
> > > > > 
> > > > > -- 
> > > > >  ---
> > > > > Ake Hedman (YAP - Yet Another Programmer)
> > > > > eurosource, Brattbergavägen 17, 820 50 LOS, Sweden
> > > > > Phone: (46) 657 413430 Cellular: (46) 73 84 84 102
> > > > > Company home: http://www.eurosource.se      
> > > > > Kryddor/Te/Kaffe: http://www.brattberg.com
> > > > > Personal homepage: http://www.eurosource.se/akhe
> > > > > Automated home: http://www.vscp.org
> > > > >
> > > >
> > >
> >
>

Re: [lpc2000] Re: Problem with watchdog

2005-12-09 by Karl Olsen

---- Original Message ----
Show quoted textHide quoted text
From: "Ken Wada" <kwada@...>
To: <lpc2000@yahoogroups.com>
Sent: Friday, December 09, 2005 9:02 PM
Subject: [lpc2000] Re: Problem with watchdog

> --- In lpc2000@yahoogroups.com, "brendanmurphy37" <brendan.murphy@i...
>> wrote:
>>
>> Can you explain why you think there's a problem with an interrupt
>> between the two writes?
>>
>> According to the User Manual: "Once 0xAA is written to
>> the WDFEED register the next operation in the Watchdog register space
>> should be a WRITE (0x55) to the WDFFED register otherwise the
>> watchdog is triggered."
>>
>> I take this to mean that the next write to the WDFEED register has to
>> be 0x55 following the 0xaa: why should it matter if this is one cycle
>> on, or 1000 cycles on (e.g. to take account of any interrupt)? I'm
>> assuming here that the interrupt itself doesn't go near the
>> watchdog.
> It makes a bit difference! If you WRITE (0x55), the processor expects
> a WRITE(0xAA) on  the very next cycle. If this is done outside an
> interrupt context, the interrupt service routine will pretty much
> guarantee that this condition is violated!

Not according to the LPC214x manual.  The second feed cycle write does not
need to be the very next processor cycle, just the next access to the
watchdog register space, which is 0xE000 0000 - 0xE000 3FFF.  So you can
write 0xAA to WDFEED, handle an interrupt that does lots of things (provided
it doesn't access any watchdog registers, or take too long), and back in the
main program write 0x55 to WDFEED.  If you write 0xAA to WDFEED, and then
write something other than 0x55 to WDFEED, or access another watchdog
register, then you have a feed error which gives an immediate reset.


>> Also, for disabling interrupts, why not just disable IRQ and FIQ in
>> the same write to the CPSR? Is there some problem with this?
> Yep...huge problem. Actually, you will see this type of problem with
> many processors/especially DSP's with fully pipelined architecture.
> The Philips User manual calls this the spurious interrupt problem.
> Actually, Philips basically took their cautionary note directly from
> the ARM users guide.

The manual mentions two unrelated kinds of spurious interrupts.  One where a
peripheral asserts an interrupt source but deasserts it again when the
program has entered the IRQ handler and asks the VIC about the interrupt
source, and one where an IRQ occurs during an MSR instruction that disables
both IRQ and FIQ.  In the latter case, FIQs are disabled during the whole
IRQ handler, and this might be inacceptably long since the foreground
program only expected FIQs to be disabled for a few cycles before reenabling
them.  Can be solved by disabling IRQs and FIQs separately.


> Gone are the good-old days of doing something like EA=0, as per 8051..
> .these pipelined architectures are a bit different when it comes to
> instruction processing.

In the ARM7TDMI without memory protection, there is little reason to use
other modes than System, IRQ, and FIQ.  Disabling all interrupts is just a
matter of

  msr cpsr_c, #0xDF    /* Set System mode, IRQ and FIQ disabled */

or, if it is a problem that FIQs can be disabled for the duration of the IRQ
handler:

  msr cpsr_c, #0x9F    /* Set System mode, IRQ disabled */
  msr cpsr_c, #0xDF    /* Set System mode, IRQ and FIQ disabled */

And enabling them:

  msr cpsr_c, #0x1F    /* Set System mode, IRQ and FIQ enabled */

Other than this specific case, the pipelining itself is very invisible to
programs.  The PC appears to be 8 ahead of the current instruction if you
read the PC register, and when returning from a FIQ or IRQ handler, you must
subtract 4 from the LR.


> Fortunately, all of these modern architectures give you a way to do
> these types of operations, (albeit with a bit more effort), via some
> software interrupt (SWI) instruction.

SWI can be useful in Thumb mode because it only takes two bytes vs. four
bytes for a BL, and it can be a win when a function is called from many
places.  It isn't necessary for doing critical sections.

Karl Olsen

Re: Problem with watchdog

2005-12-09 by brendanmurphy37

Karl,

Thanks for this: I was worried I'd been misreading the manual in 
someway, or missing something.

We don't turn interrupts off to feed the watchdog, as both 
conditions (short interrupts and not touching the watchdog registers 
in any interrupt handler) are both met. Our watchdog time is 1 
second, by the way: if an interrupt ran for this length of time, I 
think it would deserve to be kicked!

I'd also agree on the interrupt points: provided you're careful with 
your interrupt dispatch code (which can be quite simple if you stick 
to supervisor, IRQ and FIQ modes as you suggest), you shouldn't have 
problems. Pipelining, as you also suggest, is pretty much 
transparent to almost all code.

As an aside, it's probably worth looking at the original ARM 
documentation if you need to look at CPU registers/interrupts in 
detail: it's much more comprehensive that that provided by Philips 
on the topic.

Brendan

--- In lpc2000@yahoogroups.com, "Karl Olsen" <kro@p...> wrote:
>
> ---- Original Message ----
> From: "Ken Wada" <kwada@a...>
> To: <lpc2000@yahoogroups.com>
> Sent: Friday, December 09, 2005 9:02 PM
> Subject: [lpc2000] Re: Problem with watchdog
> 
> > --- In lpc2000@yahoogroups.com, "brendanmurphy37" 
<brendan.murphy@i...
> >> wrote:
> >>
> >> Can you explain why you think there's a problem with an 
interrupt
> >> between the two writes?
> >>
> >> According to the User Manual: "Once 0xAA is written to
> >> the WDFEED register the next operation in the Watchdog register 
space
> >> should be a WRITE (0x55) to the WDFFED register otherwise the
> >> watchdog is triggered."
> >>
> >> I take this to mean that the next write to the WDFEED register 
has to
> >> be 0x55 following the 0xaa: why should it matter if this is one 
cycle
> >> on, or 1000 cycles on (e.g. to take account of any interrupt)? 
I'm
> >> assuming here that the interrupt itself doesn't go near the
> >> watchdog.
> > It makes a bit difference! If you WRITE (0x55), the processor 
expects
> > a WRITE(0xAA) on  the very next cycle. If this is done outside an
> > interrupt context, the interrupt service routine will pretty much
> > guarantee that this condition is violated!
> 
> Not according to the LPC214x manual.  The second feed cycle write 
does not
> need to be the very next processor cycle, just the next access to 
the
> watchdog register space, which is 0xE000 0000 - 0xE000 3FFF.  So 
you can
> write 0xAA to WDFEED, handle an interrupt that does lots of things 
(provided
> it doesn't access any watchdog registers, or take too long), and 
back in the
> main program write 0x55 to WDFEED.  If you write 0xAA to WDFEED, 
and then
> write something other than 0x55 to WDFEED, or access another 
watchdog
> register, then you have a feed error which gives an immediate 
reset.
> 
> 
> >> Also, for disabling interrupts, why not just disable IRQ and 
FIQ in
> >> the same write to the CPSR? Is there some problem with this?
> > Yep...huge problem. Actually, you will see this type of problem 
with
> > many processors/especially DSP's with fully pipelined 
architecture.
> > The Philips User manual calls this the spurious interrupt 
problem.
> > Actually, Philips basically took their cautionary note directly 
from
> > the ARM users guide.
> 
> The manual mentions two unrelated kinds of spurious interrupts.  
One where a
> peripheral asserts an interrupt source but deasserts it again when 
the
> program has entered the IRQ handler and asks the VIC about the 
interrupt
> source, and one where an IRQ occurs during an MSR instruction that 
disables
> both IRQ and FIQ.  In the latter case, FIQs are disabled during 
the whole
> IRQ handler, and this might be inacceptably long since the 
foreground
> program only expected FIQs to be disabled for a few cycles before 
reenabling
> them.  Can be solved by disabling IRQs and FIQs separately.
> 
> 
> > Gone are the good-old days of doing something like EA=0, as per 
8051..
> > .these pipelined architectures are a bit different when it comes 
to
> > instruction processing.
> 
> In the ARM7TDMI without memory protection, there is little reason 
to use
> other modes than System, IRQ, and FIQ.  Disabling all interrupts 
is just a
> matter of
> 
>   msr cpsr_c, #0xDF    /* Set System mode, IRQ and FIQ disabled */
> 
> or, if it is a problem that FIQs can be disabled for the duration 
of the IRQ
> handler:
> 
>   msr cpsr_c, #0x9F    /* Set System mode, IRQ disabled */
>   msr cpsr_c, #0xDF    /* Set System mode, IRQ and FIQ disabled */
> 
> And enabling them:
> 
>   msr cpsr_c, #0x1F    /* Set System mode, IRQ and FIQ enabled */
> 
> Other than this specific case, the pipelining itself is very 
invisible to
> programs.  The PC appears to be 8 ahead of the current instruction 
if you
> read the PC register, and when returning from a FIQ or IRQ 
handler, you must
> subtract 4 from the LR.
> 
> 
> > Fortunately, all of these modern architectures give you a way to 
do
> > these types of operations, (albeit with a bit more effort), via 
some
> > software interrupt (SWI) instruction.
> 
> SWI can be useful in Thumb mode because it only takes two bytes 
vs. four
> bytes for a BL, and it can be a win when a function is called from 
many
Show quoted textHide quoted text
> places.  It isn't necessary for doing critical sections.
> 
> Karl Olsen
>

Re: Problem with watchdog

2005-12-09 by Ken Wada

ok...
I can surely tell you this...
I had the Watchdog working perfectly, until I started adding interrupt 
support, (mainly device drivers for the UART). After days of pulling 
my hair out, and interpreting the UM for the LPC2214 as a lawyer would 
do; it occured to me that the UM says 'feed 0x55 then 0xAA' It made 
absolutely no mentioned about what may happen if the process got 
preempted by an interrupt...

Then alas; when I installed my 1st interrupt service routine; all 
worked fine, for a few hours, and sometimes for a couple of days...

Then my clients started complaining about 'these spurious reset 
events'. They demanded that I fix the problem right away.

SO...
I came to this forum: AND I saw this:
message #5470 ---> Please also read all the threads that spawned from 
this message.

Quickly, I wrappered the WDOG pet thing with my over-engineered SWI 
service...(to keep any chance of those spurious interrupts thing from 
happening)

AND...
It has been working fine now with no glitches for about 9 months now.

As a side note: from what I can see, you my be able to disable and 
enable interrupts from the main body of your code by writing to the 
CPSR...

The big problem I have with this is that when you execute the MSR 
instruction...the ARM architecture manual clearly states that there 
may be a chance of the CPSR contents being copied into the interrupt 
service CPSR_shadow with both the IRQ and FIQ bits disabled.

You know...the probability of this type of occurence happening, in a 
real system, is practically nil.

Therefore, I decided to use the more ioctl() style of interfacing to 
the device drivers using the SWI mechanism... and letting the ARM 
pipeline and state machine sort out all the details... in terms of 
queueing and such.

The counter-side to my over-engineered approach is that it requires a 
bit more code, and is implemented more like a immutable IOCTL() device 
driver.

The flipside to this argument, is that the IOCTL() SWI protected thing 
is pretty much guaranteed to work...

Yes, I know that what I am doing is not elegant, and perhaps a bit 
over-engineered and maybe, in the long run unnecessary....

But, I have been bitten too many times with issues such as this; 
thereforem my cautious approach.

So...you are quite correct Brendan; there really is nothing 
specifically staing the fact that you need to stuff those two WDT 
values back-to-back in the Philips UM.

However, this appears to not be a new issue within this forum. In 
fact, this is how I found out that this is an issue to begin with.

Through this forum!!! There appears to be many other 'real world' 
users out there that have had exactly the same experience as I have on 
regards to this issue.

Again...about the interrupts...basically I am coding all my protected 
stuff using the well-known IOCTL() model wrappered within an SWI 
interface...Instead of 'trying' different things...There was enough 
stated in the ARM reference manual, and the Philips UM that got me 
really paranoid about the whole thing....> so...> I decided that 
caution was the best approach, and took the more circuitous...but 
guarranteed to work approach for affecting the driver interface to an 
ISR.

By the way; if you look at the Philips interrupt-driven UART ISR, 
(here in this forum, under files); they took exactly the same approach 
in interfacing the main thread with the UART variables....They 
protected it using an SWI wrapper!!!

If it is good enough for Philips...I guess it probably is good enough 
for me

Besides; I already understand and know the IOCTL()/SWI model; this 
approach to device drivers is well established and well known.

My 1st exposure to this model came from analyzing all of that Borland 
MSDOS code that ran on those old x86 machines!

Ken Wada

--- In lpc2000@yahoogroups.com, "brendanmurphy37" <brendan.murphy@i...
> wrote:
>
> 
> Ken,
> 
> I'm still curous about your statement "the processor expects
> a WRITE(0xAA) on the very next cycle". Where is this documented? It 
> may be true, but if so, I'd say it contradicts the quote I took from 
> the User Manual (for the LPC213x parts). Or am I misreading what it 
> says?
> 
> It's a fairly important point: if the feed has to be done in two 
> adjacent CPU cycles, you're forced to use assembler apart from 
> anything else, in order to do the back-to-back write reliably (I've 
> checked the assembler o/p from our own code, and it does, but you 
> can't rely on this: all you need is to change the revision of the 
> compiler or have a new optimsaition setting and thinmgs can fall 
> apart).
> 
> On the other point: you're quite right - there's plenty of "gotchas" 
> with ARM interrupts. It's been a while since I looked at this, but I 
> seem to recall spending at least a few days armed with a stack of 
> ARM books/manuals etc. (if you'll forgive the pun) to get our 
> interrupt handling code to a state we were happy with it. Funny how 
> you forget such things... I think what prompted my question was the 
> implication that you somehow couldn't set both bits at the same 
> time. As the other response on this points out, you can of course, 
> and it works, but maybe not in quite the way you'd expect.....
> 
> I'd apreciate an answer on the watchdog issue though, as it's very 
> much a live issue with us at the moment.
> 
> Regards
> Brendan
> 
> 
> --- In lpc2000@yahoogroups.com, "Ken Wada" <kwada@a...> wrote:
> >
> > --- In lpc2000@...m, "brendanmurphy37" 
> <brendan.murphy@i...
> > > wrote:
> > >
> > > 
> > > Ken,
> > > 
> > > Can you explain why you think there's a problem with an 
> interrupt 
> > > between the two writes?
> > > 
> > > According to the User Manual: "Once 0xAA is written to
> > > the WDFEED register the next operation in the Watchdog register 
> > space 
> > > should be a WRITE (0x55) to the WDFFED register otherwise the 
> > > watchdog is triggered."
> > > 
> > > I take this to mean that the next write to the WDFEED register 
> has 
> > to 
> > > be 0x55 following the 0xaa: why should it matter if this is one 
> > cycle 
> > > on, or 1000 cycles on (e.g. to take account of any interrupt)? 
> I'm 
> > > assuming here that the interrupt itself doesn't go near the 
> > watchdog.
> > It makes a bit difference! If you WRITE (0x55), the processor 
> expects 
> > a WRITE(0xAA) on  the very next cycle. If this is done outside an 
> > interrupt context, the interrupt service routine will pretty much 
> > guarantee that this condition is violated!
> > 
> > > 
> > > Also, for disabling interrupts, why not just disable IRQ and FIQ 
> in 
> > > the same write to the CPSR? Is there some problem with this?
> > Yep...huge problem. Actually, you will see this type of problem 
> with 
> > many processors/especially DSP's with fully pipelined 
> architecture. 
> > The Philips User manual calls this the spurious interrupt problem. 
> > Actually, Philips basically took their cautionary note directly 
> from 
> > the ARM users guide.
> > 
> > Gone are the good-old days of doing something like EA=0, as per 
> 8051..
> > .these pipelined architectures are a bit different when it comes 
> to 
> > instruction processing.
> > 
> > Fortunately, all of these modern architectures give you a way to 
> do 
> > these types of operations, (albeit with a bit more effort), via 
> some 
> > software interrupt (SWI) instruction.
> > 
> > My 1st encounter with this was with the Intel 80386 chip. This 
> chip 
> > had an instruction pipeline, and I had to use the int86() SWI 
> command 
> > in order to properly code up the atomic sections.
> > 
> > Ken Wada
> > > 
> > > regards
> > > Brendan
> > >  
> > > 
> > > --- In lpc2000@yahoogroups.com, "Ken Wada" <kwada@a...> wrote:
> > > >
> > > > Basically, your method works fine...
> > > > UNTIL: you start adding interrupt service routines!
> > > > 
> > > > This is why:
> > > > void WDOG_pet()
> > > > {
> > > > WDFEED = 0xAA;
> > > > /*             Interrupt occurs here...> dog will NOT pet 
> > > properly!!! 
> > > > ***/
> > > > WDFEED = 0x55;
> > > > }
> > > > 
> > > > /**** example uses Keil compiler directives ***/
> > > > /********** The following is what I wound up doing, (gotta 
> avoid 
> > > that 
> > > > spurious interrupt issue with the ARM also!!! ***/
> > > > 
> > > > /**** The actual interface that everybody uses ***/
> > > > void WDOG_pet (void)
> > > > {
> > > >     SYSSWI_service (12,0,0,0);
> > > > }
> > > > 
> > > > /***** How the SYSSWI_service works, (based on SWI) ***/
> > > > unsigned SYSSWI_service (SYSSWI opcode, int id, void *pObj, 
> > > unsigned 
> > > > _user1) __swi(12)
> > > > {
> > > >     switch (opcode)
> > > >     {
> > > >       case SYSSWI_WDOGPET:
> > > >         SYSSWI_watchDogPet ();
> > > >         break;
> > > >       ...
> > > >     }
> > > >     return (0);
> > > > }
> > > > 
> > > > /***** How the SYSSWI_watchDogPet () works ***/
> > > > static void SYSSWI_watchDogPet (void)
> > > > {
> > > >     ARM_disableFIQ ();                /* make sure FIQ is 
> > > disabled     
> > > >      */
> > > >     WDFEED  = 0xAA;
> > > >     WDFEED  = 0x55;
> > > >     ARM_enableFIQ ();                 /* re-enable the 
> > > FIQ             
> > > >      */
> > > > }
> > > > 
> > > > /***** The IRQ is automatically disabled by vectoring to the 
> SWI..
> > .
> > > > however, you need to make the operation atomic with respect to 
> > FIQ, 
> > > > which is NOT disabled ***/
> > > > 
> > > > PUBLIC  ARM_disableFIQ?A ; interface is ARM mode
> > > > 
> > > > ARM_disableFIQ?A  PROC  CODE32
> > > >       MRS   R0,CPSR
> > > >       ORR   R0,R0,#0x0040                   ; Mask just the 
FIQ
Show quoted textHide quoted text
> > > >       MSR   CPSR_c,R0
> > > >       BX    R14
> > > > 
> > > >       ENDP
> > > > 
> > > > PUBLIC  ARM_enableFIQ?A ; interface is ARM mode
> > > > 
> > > > ARM_enableFIQ?A  PROC  CODE32
> > > >       MRS   R0,CPSR
> > > >       BIC   R0,R0,#0x0040                   ; Enable just the 
> FIQ
> > > >       MSR   CPSR_c,R0
> > > >       BX    R14
> > > > 
> > > >       ENDP
> > > > END
> > > > 
> > > > 
> > > > --- In lpc2000@yahoogroups.com, "Ake Hedman, eurosource" 
> > > <akhe@b...> 
> > > > wrote:
> > > > >
> > > > > Hi all.
> > > > > 
> > > > > I am trying to enable the watchdog but the result is a total 
> > hang 
> > > of 
> > > > the 
> > > > > board. Not even the bootloader is possible to reach after 
> the 
> > > crash 
> > > > and 
> > > > > I have to reapply power with P0.14 low to get access to the 
> > > > botloader 
> > > > > again. Reset is not enough.
> > > > > 
> > > > > The code to initialize the watchdog is
> > > > > 
> > > > >     // initialize the watchdog timer
> > > > >     WDTC = 0xffffffff; // 
> 15000000;                        // 
> > One 
> > > > second 
> > > > > = 15000000
> > > > >     WDMOD = WDEN | WDRESET;                    // Activate 
> > > watchdog
> > > > >     WDFEED = 0xAA; WDFEED = 0x55;
> > > > > 
> > > > > I must have misunderstood the WD functionality. What am I 
> doing 
> > > > wrong? 
> > > > > In the above code the watchdog should not trigger until 5 
> > minutes 
> > > > > elapsed so even if a vector should be wrong the code that 
> follow 
> > > > should 
> > > > > run for a while but as soon as I write to the WDMOD register 
> I 
> > > get a 
> > > > hang.
> > > > > 
> > > > > /Ake
> > > > > 
> > > > > -- 
> > > > >  ---
> > > > > Ake Hedman (YAP - Yet Another Programmer)
> > > > > eurosource, Brattbergavägen 17, 820 50 LOS, Sweden
> > > > > Phone: (46) 657 413430 Cellular: (46) 73 84 84 102
> > > > > Company home: http://www.eurosource.se      
> > > > > Kryddor/Te/Kaffe: http://www.brattberg.com
> > > > > Personal homepage: http://www.eurosource.se/akhe
> > > > > Automated home: http://www.vscp.org
> > > > >
> > > >
> > >
> >
>

Re: [lpc2000] Re: Problem with watchdog

2005-12-10 by Karl Olsen

---- Original Message ----
Show quoted textHide quoted text
From: "Ken Wada" <kwada@...>
To: <lpc2000@yahoogroups.com>
Sent: Saturday, December 10, 2005 12:17 AM
Subject: [lpc2000] Re: Problem with watchdog

> ok...
> I can surely tell you this...
> I had the Watchdog working perfectly, until I started adding interrupt
> support, (mainly device drivers for the UART). After days of pulling
> my hair out, and interpreting the UM for the LPC2214 as a lawyer would
> do; it occured to me that the UM says 'feed 0x55 then 0xAA' It made
> absolutely no mentioned about what may happen if the process got
> preempted by an interrupt...
> 
> Then alas; when I installed my 1st interrupt service routine; all
> worked fine, for a few hours, and sometimes for a couple of days...
> 
> Then my clients started complaining about 'these spurious reset
> events'. They demanded that I fix the problem right away.
> 
> SO...
> I came to this forum: AND I saw this:
> message #5470 ---> Please also read all the threads that spawned from
> this message.

OK, it certainly looks like an interrupt between the feed writes will reset
the CPU.  All the manuals, including the new LPC2103 manual, have the same
wording about WDFEED.  philips_apps, is this a bug in the manuals or in the
chips?

Karl Olsen

Re: Problem with watchdog

2005-12-10 by Ken Wada

I have been wondering about that myself.

If you look very closely at the past threads, in this forum, others 
have been wondering about this also.

I have scoured all the LPC2xxx errata; and I have found no mention of 
this either.

It could very well be that certain revisions of the LPC22xx silicon 
may have this feature, whereas the later revisions may not, or that 
there is an errata in the UM.

In either case, I am very happy with the current state of affairs with 
my customer's projects using the LPC22xx...In that they all work 
pretty much flawlessly, (where the WDT is concerned).

To date, the best information I have gotten, on some of the 'features 
of the LPC22xx' has come from this forum.

These caveats include:
1.  WDT issues
2.  PLL setup and the VPB divider errata
3.  Changing between default level-triggered vs. edge triggered 
interrupts, (don't do this!)
4.  Changing between default low-level vs. high-level interrupt 
source, (again, don't do this!)
5.  Of course, the oft-repeated spurious interrupt issue. There was 
enough within the manuals, and this forum to scare me into doing 
something over-engineered (in my opinion)...but is guaranteed to work.

What I have done, in general, is read all the threads on these various 
topics, and try to ascertain how much trouble people out there are 
having with the various LPC2xxx issues.

Ken Wada

--- In lpc2000@yahoogroups.com, "Karl Olsen" <kro@p...> wrote:
>
> ---- Original Message ----
> From: "Ken Wada" <kwada@a...>
> To: <lpc2000@yahoogroups.com>
> Sent: Saturday, December 10, 2005 12:17 AM
> Subject: [lpc2000] Re: Problem with watchdog
> 
> > ok...
> > I can surely tell you this...
> > I had the Watchdog working perfectly, until I started adding 
interrupt
> > support, (mainly device drivers for the UART). After days of 
pulling
> > my hair out, and interpreting the UM for the LPC2214 as a lawyer 
would
> > do; it occured to me that the UM says 'feed 0x55 then 0xAA' It 
made
> > absolutely no mentioned about what may happen if the process got
> > preempted by an interrupt...
> > 
> > Then alas; when I installed my 1st interrupt service routine; all
> > worked fine, for a few hours, and sometimes for a couple of days..
.
> > 
> > Then my clients started complaining about 'these spurious reset
> > events'. They demanded that I fix the problem right away.
> > 
> > SO...
> > I came to this forum: AND I saw this:
> > message #5470 ---> Please also read all the threads that spawned 
from
> > this message.
> 
> OK, it certainly looks like an interrupt between the feed writes 
will reset
> the CPU.  All the manuals, including the new LPC2103 manual, have 
the same
> wording about WDFEED.  philips_apps, is this a bug in the manuals or 
in the
Show quoted textHide quoted text
> chips?
> 
> Karl Olsen
>

[lpc2000] Re: Problem with watchdog

2005-12-10 by Robert Adsett

At 10:02 PM 12/9/05 +0000, Ken Wada wrote:
>Asynchronously turning off and on interrupts in the main body of your
>code is problematic. Instead of tempting fate; I decided to play the
>overly-cautious role. It is the following excerpt from the Philips
>User Manual that gave me pause:
>
>"Although the example shows both IRQ and FIQ interrupts being
>disabled, similar behavior occurs when only one of the two
>interrupt types is being disabled. The fact that the core processes
>the IRQ after completion of the MSR instruction which disables
>IRQs does not normally cause a problem, since an interrupt arriving
>just one cycle earlier would be expected to be taken. When
>the interrupt routine returns with an instruction like:
>SUBS pc, lr, #4
>the SPSR_IRQ is restored to the CPSR. The CPSR will now have the I bit
>and F bit set, and therefore execution will continue
>with all interrupts disabled."

Which, of course,  is what it should do since that is what  was being asked 
of it.

IE the sequence

disable interrupts
critical code
restore interrupts

will always result in the interrupts being re-enabled at the end.

The only problems that occur are if the code following the interrupt 
disable sequence is using tricky flag manipulation to determine if it is in 
an interrupt or not, or if you are using both IRQs and FIQs.  The later 
case strikes me as far more likely and there are several simple 
work-arounds for that. the simplest being to disable the IRQ and FIQ in 
sequence rather than both at once where you need critical region protection.

However if you either don't use the FIQ or don't care if it is occasionally 
disabled during an IRQ the status register manipulation should be safe.  I 
don't see any reason for the interrupt detection code to be much more than 
a parlour trick, although I could be convinced otherwise.

Robert

" 'Freedom' has no meaning of itself.  There are always restrictions,   be 
they legal, genetic, or physical.  If you don't believe me, try to chew a 
radio signal. "  -- Kelvin Throop, III
http://www.aeolusdevelopment.com/

Re: Problem with watchdog

2005-12-10 by brendanmurphy37

Ken,

Thanks for the reference to the previous discussion on this: it's 
exactly what I was looking for (confirmation/proof that there is 
indeed a problem).

By the way, I think you may have misunderstood my comment on the 
interrupt issue. No need to explain where you're coming from: far 
from suggesting you change, I'd strongly advise keeping what you 
have, if it works and causes no problems. I've seen too many cases 
of (inexperienced) engineers tweaking something that works to "make 
it more efficient", only to see it explode in people's faces further 
down the line. As you point out, there's nothing better then the 
knowledge of maybe tens or hundreds of thousands of units in the 
field to focus the mind on reliability as THE primary consideration.

It was more for the benefit of others who may be reading to point 
out there are much simpler ways of working around the quirks of ARM 
interrupts (which also give 100% reliability). Personally, I find 
this forum very useful, particularly in the mix of people 
contributing, from hobbyists to professionals, each bringing a 
particular perspective. 

One thing I've learnt is that there is almost never one correct 
solution to a problem. In fact, if you can't think of two or three 
solutions to a particular problem, you probably don't understand it 
well enough in the first place.

My own lesson from this is that I should really have searched the 
message archive for watchdog issues before starting.

I think it's a big help too to have Philips actively monitor this 
forum: I've no doubt they will react positively to this and other 
issues, and provide ammended or new documantation to describe the 
various issues with the parts.

Brendan


--- In lpc2000@yahoogroups.com, "Ken Wada" <kwada@a...> wrote:
>
> ok...
> I can surely tell you this...
> I had the Watchdog working perfectly, until I started adding 
interrupt 
> support, (mainly device drivers for the UART). After days of 
pulling 
> my hair out, and interpreting the UM for the LPC2214 as a lawyer 
would 
> do; it occured to me that the UM says 'feed 0x55 then 0xAA' It 
made 
> absolutely no mentioned about what may happen if the process got 
> preempted by an interrupt...
> 
> Then alas; when I installed my 1st interrupt service routine; all 
> worked fine, for a few hours, and sometimes for a couple of days...
> 
> Then my clients started complaining about 'these spurious reset 
> events'. They demanded that I fix the problem right away.
> 
> SO...
> I came to this forum: AND I saw this:
> message #5470 ---> Please also read all the threads that spawned 
from 
> this message.
> 
> Quickly, I wrappered the WDOG pet thing with my over-engineered 
SWI 
> service...(to keep any chance of those spurious interrupts thing 
from 
> happening)
> 
> AND...
> It has been working fine now with no glitches for about 9 months 
now.
> 
> As a side note: from what I can see, you my be able to disable and 
> enable interrupts from the main body of your code by writing to 
the 
> CPSR...
> 
> The big problem I have with this is that when you execute the MSR 
> instruction...the ARM architecture manual clearly states that 
there 
> may be a chance of the CPSR contents being copied into the 
interrupt 
> service CPSR_shadow with both the IRQ and FIQ bits disabled.
> 
> You know...the probability of this type of occurence happening, in 
a 
> real system, is practically nil.
> 
> Therefore, I decided to use the more ioctl() style of interfacing 
to 
> the device drivers using the SWI mechanism... and letting the ARM 
> pipeline and state machine sort out all the details... in terms of 
> queueing and such.
> 
> The counter-side to my over-engineered approach is that it 
requires a 
> bit more code, and is implemented more like a immutable IOCTL() 
device 
> driver.
> 
> The flipside to this argument, is that the IOCTL() SWI protected 
thing 
> is pretty much guaranteed to work...
> 
> Yes, I know that what I am doing is not elegant, and perhaps a bit 
> over-engineered and maybe, in the long run unnecessary....
> 
> But, I have been bitten too many times with issues such as this; 
> thereforem my cautious approach.
> 
> So...you are quite correct Brendan; there really is nothing 
> specifically staing the fact that you need to stuff those two WDT 
> values back-to-back in the Philips UM.
> 
> However, this appears to not be a new issue within this forum. In 
> fact, this is how I found out that this is an issue to begin with.
> 
> Through this forum!!! There appears to be many other 'real world' 
> users out there that have had exactly the same experience as I 
have on 
> regards to this issue.
> 
> Again...about the interrupts...basically I am coding all my 
protected 
> stuff using the well-known IOCTL() model wrappered within an SWI 
> interface...Instead of 'trying' different things...There was 
enough 
> stated in the ARM reference manual, and the Philips UM that got me 
> really paranoid about the whole thing....> so...> I decided that 
> caution was the best approach, and took the more circuitous...but 
> guarranteed to work approach for affecting the driver interface to 
an 
> ISR.
> 
> By the way; if you look at the Philips interrupt-driven UART ISR, 
> (here in this forum, under files); they took exactly the same 
approach 
> in interfacing the main thread with the UART variables....They 
> protected it using an SWI wrapper!!!
> 
> If it is good enough for Philips...I guess it probably is good 
enough 
> for me
> 
> Besides; I already understand and know the IOCTL()/SWI model; this 
> approach to device drivers is well established and well known.
> 
> My 1st exposure to this model came from analyzing all of that 
Borland 
> MSDOS code that ran on those old x86 machines!
> 
> Ken Wada
> 
> --- In lpc2000@yahoogroups.com, "brendanmurphy37" 
<brendan.murphy@i...
> > wrote:
> >
> > 
> > Ken,
> > 
> > I'm still curous about your statement "the processor expects
> > a WRITE(0xAA) on the very next cycle". Where is this documented? 
It 
> > may be true, but if so, I'd say it contradicts the quote I took 
from 
> > the User Manual (for the LPC213x parts). Or am I misreading what 
it 
> > says?
> > 
> > It's a fairly important point: if the feed has to be done in two 
> > adjacent CPU cycles, you're forced to use assembler apart from 
> > anything else, in order to do the back-to-back write reliably 
(I've 
> > checked the assembler o/p from our own code, and it does, but 
you 
> > can't rely on this: all you need is to change the revision of 
the 
> > compiler or have a new optimsaition setting and thinmgs can fall 
> > apart).
> > 
> > On the other point: you're quite right - there's plenty 
of "gotchas" 
> > with ARM interrupts. It's been a while since I looked at this, 
but I 
> > seem to recall spending at least a few days armed with a stack 
of 
> > ARM books/manuals etc. (if you'll forgive the pun) to get our 
> > interrupt handling code to a state we were happy with it. Funny 
how 
> > you forget such things... I think what prompted my question was 
the 
> > implication that you somehow couldn't set both bits at the same 
> > time. As the other response on this points out, you can of 
course, 
> > and it works, but maybe not in quite the way you'd expect.....
> > 
> > I'd apreciate an answer on the watchdog issue though, as it's 
very 
> > much a live issue with us at the moment.
> > 
> > Regards
> > Brendan
> > 
> > 
> > --- In lpc2000@yahoogroups.com, "Ken Wada" <kwada@a...> wrote:
> > >
> > > --- In lpc2000@yahoogroups.com, "brendanmurphy37" 
> > <brendan.murphy@i...
> > > > wrote:
> > > >
> > > > 
> > > > Ken,
> > > > 
> > > > Can you explain why you think there's a problem with an 
> > interrupt 
> > > > between the two writes?
> > > > 
> > > > According to the User Manual: "Once 0xAA is written to
> > > > the WDFEED register the next operation in the Watchdog 
register 
> > > space 
> > > > should be a WRITE (0x55) to the WDFFED register otherwise 
the 
> > > > watchdog is triggered."
> > > > 
> > > > I take this to mean that the next write to the WDFEED 
register 
> > has 
> > > to 
> > > > be 0x55 following the 0xaa: why should it matter if this is 
one 
> > > cycle 
> > > > on, or 1000 cycles on (e.g. to take account of any 
interrupt)? 
> > I'm 
> > > > assuming here that the interrupt itself doesn't go near the 
> > > watchdog.
> > > It makes a bit difference! If you WRITE (0x55), the processor 
> > expects 
> > > a WRITE(0xAA) on  the very next cycle. If this is done outside 
an 
> > > interrupt context, the interrupt service routine will pretty 
much 
> > > guarantee that this condition is violated!
> > > 
> > > > 
> > > > Also, for disabling interrupts, why not just disable IRQ and 
FIQ 
> > in 
> > > > the same write to the CPSR? Is there some problem with this?
> > > Yep...huge problem. Actually, you will see this type of 
problem 
> > with 
> > > many processors/especially DSP's with fully pipelined 
> > architecture. 
> > > The Philips User manual calls this the spurious interrupt 
problem. 
> > > Actually, Philips basically took their cautionary note 
directly 
> > from 
> > > the ARM users guide.
> > > 
> > > Gone are the good-old days of doing something like EA=0, as 
per 
> > 8051..
> > > .these pipelined architectures are a bit different when it 
comes 
> > to 
> > > instruction processing.
> > > 
> > > Fortunately, all of these modern architectures give you a way 
to 
> > do 
> > > these types of operations, (albeit with a bit more effort), 
via 
> > some 
> > > software interrupt (SWI) instruction.
> > > 
> > > My 1st encounter with this was with the Intel 80386 chip. This 
> > chip 
> > > had an instruction pipeline, and I had to use the int86() SWI 
> > command 
> > > in order to properly code up the atomic sections.
> > > 
> > > Ken Wada
> > > > 
> > > > regards
> > > > Brendan
> > > >  
> > > > 
> > > > --- In lpc2000@yahoogroups.com, "Ken Wada" <kwada@a...> 
wrote:
> > > > >
> > > > > Basically, your method works fine...
> > > > > UNTIL: you start adding interrupt service routines!
> > > > > 
> > > > > This is why:
> > > > > void WDOG_pet()
> > > > > {
> > > > > WDFEED = 0xAA;
> > > > > /*             Interrupt occurs here...> dog will NOT pet 
> > > > properly!!! 
> > > > > ***/
> > > > > WDFEED = 0x55;
> > > > > }
> > > > > 
> > > > > /**** example uses Keil compiler directives ***/
> > > > > /********** The following is what I wound up doing, (gotta 
> > avoid 
> > > > that 
> > > > > spurious interrupt issue with the ARM also!!! ***/
> > > > > 
> > > > > /**** The actual interface that everybody uses ***/
> > > > > void WDOG_pet (void)
> > > > > {
> > > > >     SYSSWI_service (12,0,0,0);
> > > > > }
> > > > > 
> > > > > /***** How the SYSSWI_service works, (based on SWI) ***/
> > > > > unsigned SYSSWI_service (SYSSWI opcode, int id, void 
*pObj, 
> > > > unsigned 
> > > > > _user1) __swi(12)
> > > > > {
> > > > >     switch (opcode)
> > > > >     {
> > > > >       case SYSSWI_WDOGPET:
> > > > >         SYSSWI_watchDogPet ();
> > > > >         break;
> > > > >       ...
> > > > >     }
> > > > >     return (0);
> > > > > }
> > > > > 
> > > > > /***** How the SYSSWI_watchDogPet () works ***/
> > > > > static void SYSSWI_watchDogPet (void)
> > > > > {
> > > > >     ARM_disableFIQ ();                /* make sure FIQ is 
> > > > disabled     
> > > > >      */
> > > > >     WDFEED  = 0xAA;
> > > > >     WDFEED  = 0x55;
> > > > >     ARM_enableFIQ ();                 /* re-enable the 
> > > > FIQ             
> > > > >      */
> > > > > }
> > > > > 
> > > > > /***** The IRQ is automatically disabled by vectoring to 
the 
> > SWI..
> > > .
> > > > > however, you need to make the operation atomic with 
respect to 
> > > FIQ, 
> > > > > which is NOT disabled ***/
> > > > > 
> > > > > PUBLIC  ARM_disableFIQ?A ; interface is ARM mode
> > > > > 
> > > > > ARM_disableFIQ?A  PROC  CODE32
> > > > >       MRS   R0,CPSR
> > > > >       ORR   R0,R0,#0x0040                   ; Mask just 
the 
> FIQ
> > > > >       MSR   CPSR_c,R0
> > > > >       BX    R14
> > > > > 
> > > > >       ENDP
> > > > > 
> > > > > PUBLIC  ARM_enableFIQ?A ; interface is ARM mode
> > > > > 
> > > > > ARM_enableFIQ?A  PROC  CODE32
> > > > >       MRS   R0,CPSR
> > > > >       BIC   R0,R0,#0x0040                   ; Enable just 
the 
> > FIQ
> > > > >       MSR   CPSR_c,R0
> > > > >       BX    R14
> > > > > 
> > > > >       ENDP
> > > > > END
> > > > > 
> > > > > 
> > > > > --- In lpc2000@yahoogroups.com, "Ake Hedman, eurosource" 
> > > > <akhe@b...> 
> > > > > wrote:
> > > > > >
> > > > > > Hi all.
> > > > > > 
> > > > > > I am trying to enable the watchdog but the result is a 
total 
> > > hang 
> > > > of 
> > > > > the 
> > > > > > board. Not even the bootloader is possible to reach 
after 
> > the 
> > > > crash 
> > > > > and 
> > > > > > I have to reapply power with P0.14 low to get access to 
the 
> > > > > botloader 
> > > > > > again. Reset is not enough.
> > > > > > 
> > > > > > The code to initialize the watchdog is
> > > > > > 
> > > > > >     // initialize the watchdog timer
> > > > > >     WDTC = 0xffffffff; // 
> > 15000000;                        // 
> > > One 
> > > > > second 
> > > > > > = 15000000
> > > > > >     WDMOD = WDEN | WDRESET;                    // 
Activate 
> > > > watchdog
> > > > > >     WDFEED = 0xAA; WDFEED = 0x55;
> > > > > > 
> > > > > > I must have misunderstood the WD functionality. What am 
I 
> > doing 
> > > > > wrong? 
> > > > > > In the above code the watchdog should not trigger until 
5 
> > > minutes 
> > > > > > elapsed so even if a vector should be wrong the code 
that 
> > follow 
> > > > > should 
> > > > > > run for a while but as soon as I write to the WDMOD 
register 
Show quoted textHide quoted text
> > I 
> > > > get a 
> > > > > hang.
> > > > > > 
> > > > > > /Ake
> > > > > > 
> > > > > > -- 
> > > > > >  ---
> > > > > > Ake Hedman (YAP - Yet Another Programmer)
> > > > > > eurosource, Brattbergavägen 17, 820 50 LOS, Sweden
> > > > > > Phone: (46) 657 413430 Cellular: (46) 73 84 84 102
> > > > > > Company home: http://www.eurosource.se      
> > > > > > Kryddor/Te/Kaffe: http://www.brattberg.com
> > > > > > Personal homepage: http://www.eurosource.se/akhe
> > > > > > Automated home: http://www.vscp.org
> > > > > >
> > > > >
> > > >
> > >
> >
>

Re: [lpc2000] Re: Problem with watchdog

2005-12-10 by Ake Hedman, eurosource

Hi and thankyou for this discussion.

I just want to confirm that my problems also go away when I turn of 
IRQ's while feeding the dog. I have just tested it on a minimalistic 
sample where I only have I2C and UART interrupts and where the problem 
starts as soon as I add the I2C code.

I will try this on my real application and report back.

You are all worth a beer on me tonight  (if I only could reach you...). 
Lets hope that Karma things works... :-)

/Ake

brendanmurphy37 wrote:

>
> Ken,
>
> Thanks for the reference to the previous discussion on this: it's
> exactly what I was looking for (confirmation/proof that there is
> indeed a problem).
>
> By the way, I think you may have misunderstood my comment on the
> interrupt issue. No need to explain where you're coming from: far
> from suggesting you change, I'd strongly advise keeping what you
> have, if it works and causes no problems. I've seen too many cases
> of (inexperienced) engineers tweaking something that works to "make
> it more efficient", only to see it explode in people's faces further
> down the line. As you point out, there's nothing better then the
> knowledge of maybe tens or hundreds of thousands of units in the
> field to focus the mind on reliability as THE primary consideration.
>
> It was more for the benefit of others who may be reading to point
> out there are much simpler ways of working around the quirks of ARM
> interrupts (which also give 100% reliability). Personally, I find
> this forum very useful, particularly in the mix of people
> contributing, from hobbyists to professionals, each bringing a
> particular perspective.
>
> One thing I've learnt is that there is almost never one correct
> solution to a problem. In fact, if you can't think of two or three
> solutions to a particular problem, you probably don't understand it
> well enough in the first place.
>
> My own lesson from this is that I should really have searched the
> message archive for watchdog issues before starting.
>
> I think it's a big help too to have Philips actively monitor this
> forum: I've no doubt they will react positively to this and other
> issues, and provide ammended or new documantation to describe the
> various issues with the parts.
>
> Brendan
>
>
> --- In lpc2000@yahoogroups.com, "Ken Wada" <kwada@a...> wrote:
> >
> > ok...
> > I can surely tell you this...
> > I had the Watchdog working perfectly, until I started adding
> interrupt
> > support, (mainly device drivers for the UART). After days of
> pulling
> > my hair out, and interpreting the UM for the LPC2214 as a lawyer
> would
> > do; it occured to me that the UM says 'feed 0x55 then 0xAA' It
> made
> > absolutely no mentioned about what may happen if the process got
> > preempted by an interrupt...
> >
> > Then alas; when I installed my 1st interrupt service routine; all
> > worked fine, for a few hours, and sometimes for a couple of days...
> >
> > Then my clients started complaining about 'these spurious reset
> > events'. They demanded that I fix the problem right away.
> >
> > SO...
> > I came to this forum: AND I saw this:
> > message #5470 ---> Please also read all the threads that spawned
> from
> > this message.
> >
> > Quickly, I wrappered the WDOG pet thing with my over-engineered
> SWI
> > service...(to keep any chance of those spurious interrupts thing
> from
> > happening)
> >
> > AND...
> > It has been working fine now with no glitches for about 9 months
> now.
> >
> > As a side note: from what I can see, you my be able to disable and
> > enable interrupts from the main body of your code by writing to
> the
> > CPSR...
> >
> > The big problem I have with this is that when you execute the MSR
> > instruction...the ARM architecture manual clearly states that
> there
> > may be a chance of the CPSR contents being copied into the
> interrupt
> > service CPSR_shadow with both the IRQ and FIQ bits disabled.
> >
> > You know...the probability of this type of occurence happening, in
> a
> > real system, is practically nil.
> >
> > Therefore, I decided to use the more ioctl() style of interfacing
> to
> > the device drivers using the SWI mechanism... and letting the ARM
> > pipeline and state machine sort out all the details... in terms of
> > queueing and such.
> >
> > The counter-side to my over-engineered approach is that it
> requires a
> > bit more code, and is implemented more like a immutable IOCTL()
> device
> > driver.
> >
> > The flipside to this argument, is that the IOCTL() SWI protected
> thing
> > is pretty much guaranteed to work...
> >
> > Yes, I know that what I am doing is not elegant, and perhaps a bit
> > over-engineered and maybe, in the long run unnecessary....
> >
> > But, I have been bitten too many times with issues such as this;
> > thereforem my cautious approach.
> >
> > So...you are quite correct Brendan; there really is nothing
> > specifically staing the fact that you need to stuff those two WDT
> > values back-to-back in the Philips UM.
> >
> > However, this appears to not be a new issue within this forum. In
> > fact, this is how I found out that this is an issue to begin with.
> >
> > Through this forum!!! There appears to be many other 'real world'
> > users out there that have had exactly the same experience as I
> have on
> > regards to this issue.
> >
> > Again...about the interrupts...basically I am coding all my
> protected
> > stuff using the well-known IOCTL() model wrappered within an SWI
> > interface...Instead of 'trying' different things...There was
> enough
> > stated in the ARM reference manual, and the Philips UM that got me
> > really paranoid about the whole thing....> so...> I decided that
> > caution was the best approach, and took the more circuitous...but
> > guarranteed to work approach for affecting the driver interface to
> an
> > ISR.
> >
> > By the way; if you look at the Philips interrupt-driven UART ISR,
> > (here in this forum, under files); they took exactly the same
> approach
> > in interfacing the main thread with the UART variables....They
> > protected it using an SWI wrapper!!!
> >
> > If it is good enough for Philips...I guess it probably is good
> enough
> > for me
> >
> > Besides; I already understand and know the IOCTL()/SWI model; this
> > approach to device drivers is well established and well known.
> >
> > My 1st exposure to this model came from analyzing all of that
> Borland
> > MSDOS code that ran on those old x86 machines!
> >
> > Ken Wada
> >
> > --- In lpc2000@yahoogroups.com, "brendanmurphy37"
> <brendan.murphy@i...
> > > wrote:
> > >
> > >
> > > Ken,
> > >
> > > I'm still curous about your statement "the processor expects
> > > a WRITE(0xAA) on the very next cycle". Where is this documented?
> It
> > > may be true, but if so, I'd say it contradicts the quote I took
> from
> > > the User Manual (for the LPC213x parts). Or am I misreading what
> it
> > > says?
> > >
> > > It's a fairly important point: if the feed has to be done in two
> > > adjacent CPU cycles, you're forced to use assembler apart from
> > > anything else, in order to do the back-to-back write reliably
> (I've
> > > checked the assembler o/p from our own code, and it does, but
> you
> > > can't rely on this: all you need is to change the revision of
> the
> > > compiler or have a new optimsaition setting and thinmgs can fall
> > > apart).
> > >
> > > On the other point: you're quite right - there's plenty
> of "gotchas"
> > > with ARM interrupts. It's been a while since I looked at this,
> but I
> > > seem to recall spending at least a few days armed with a stack
> of
> > > ARM books/manuals etc. (if you'll forgive the pun) to get our
> > > interrupt handling code to a state we were happy with it. Funny
> how
> > > you forget such things... I think what prompted my question was
> the
> > > implication that you somehow couldn't set both bits at the same
> > > time. As the other response on this points out, you can of
> course,
> > > and it works, but maybe not in quite the way you'd expect.....
> > >
> > > I'd apreciate an answer on the watchdog issue though, as it's
> very
> > > much a live issue with us at the moment.
> > >
> > > Regards
> > > Brendan
> > >
> > >
> > > --- In lpc2000@yahoogroups.com, "Ken Wada" <kwada@a...> wrote:
> > > >
> > > > --- In lpc2000@yahoogroups.com, "brendanmurphy37"
> > > <brendan.murphy@i...
> > > > > wrote:
> > > > >
> > > > >
> > > > > Ken,
> > > > >
> > > > > Can you explain why you think there's a problem with an
> > > interrupt
> > > > > between the two writes?
> > > > >
> > > > > According to the User Manual: "Once 0xAA is written to
> > > > > the WDFEED register the next operation in the Watchdog
> register
> > > > space
> > > > > should be a WRITE (0x55) to the WDFFED register otherwise
> the
> > > > > watchdog is triggered."
> > > > >
> > > > > I take this to mean that the next write to the WDFEED
> register
> > > has
> > > > to
> > > > > be 0x55 following the 0xaa: why should it matter if this is
> one
> > > > cycle
> > > > > on, or 1000 cycles on (e.g. to take account of any
> interrupt)?
> > > I'm
> > > > > assuming here that the interrupt itself doesn't go near the
> > > > watchdog.
> > > > It makes a bit difference! If you WRITE (0x55), the processor
> > > expects
> > > > a WRITE(0xAA) on  the very next cycle. If this is done outside
> an
> > > > interrupt context, the interrupt service routine will pretty
> much
> > > > guarantee that this condition is violated!
> > > >
> > > > >
> > > > > Also, for disabling interrupts, why not just disable IRQ and
> FIQ
> > > in
> > > > > the same write to the CPSR? Is there some problem with this?
> > > > Yep...huge problem. Actually, you will see this type of
> problem
> > > with
> > > > many processors/especially DSP's with fully pipelined
> > > architecture.
> > > > The Philips User manual calls this the spurious interrupt
> problem.
> > > > Actually, Philips basically took their cautionary note
> directly
> > > from
> > > > the ARM users guide.
> > > >
> > > > Gone are the good-old days of doing something like EA=0, as
> per
> > > 8051..
> > > > .these pipelined architectures are a bit different when it
> comes
> > > to
> > > > instruction processing.
> > > >
> > > > Fortunately, all of these modern architectures give you a way
> to
> > > do
> > > > these types of operations, (albeit with a bit more effort),
> via
> > > some
> > > > software interrupt (SWI) instruction.
> > > >
> > > > My 1st encounter with this was with the Intel 80386 chip. This
> > > chip
> > > > had an instruction pipeline, and I had to use the int86() SWI
> > > command
> > > > in order to properly code up the atomic sections.
> > > >
> > > > Ken Wada
> > > > >
> > > > > regards
> > > > > Brendan
> > > > > 
> > > > >
> > > > > --- In lpc2000@yahoogroups.com, "Ken Wada" <kwada@a...>
> wrote:
> > > > > >
> > > > > > Basically, your method works fine...
> > > > > > UNTIL: you start adding interrupt service routines!
> > > > > >
> > > > > > This is why:
> > > > > > void WDOG_pet()
> > > > > > {
> > > > > > WDFEED = 0xAA;
> > > > > > /*             Interrupt occurs here...> dog will NOT pet
> > > > > properly!!!
> > > > > > ***/
> > > > > > WDFEED = 0x55;
> > > > > > }
> > > > > >
> > > > > > /**** example uses Keil compiler directives ***/
> > > > > > /********** The following is what I wound up doing, (gotta
> > > avoid
> > > > > that
> > > > > > spurious interrupt issue with the ARM also!!! ***/
> > > > > >
> > > > > > /**** The actual interface that everybody uses ***/
> > > > > > void WDOG_pet (void)
> > > > > > {
> > > > > >     SYSSWI_service (12,0,0,0);
> > > > > > }
> > > > > >
> > > > > > /***** How the SYSSWI_service works, (based on SWI) ***/
> > > > > > unsigned SYSSWI_service (SYSSWI opcode, int id, void
> *pObj,
> > > > > unsigned
> > > > > > _user1) __swi(12)
> > > > > > {
> > > > > >     switch (opcode)
> > > > > >     {
> > > > > >       case SYSSWI_WDOGPET:
> > > > > >         SYSSWI_watchDogPet ();
> > > > > >         break;
> > > > > >       ...
> > > > > >     }
> > > > > >     return (0);
> > > > > > }
> > > > > >
> > > > > > /***** How the SYSSWI_watchDogPet () works ***/
> > > > > > static void SYSSWI_watchDogPet (void)
> > > > > > {
> > > > > >     ARM_disableFIQ ();                /* make sure FIQ is
> > > > > disabled    
> > > > > >      */
> > > > > >     WDFEED  = 0xAA;
> > > > > >     WDFEED  = 0x55;
> > > > > >     ARM_enableFIQ ();                 /* re-enable the
> > > > > FIQ            
> > > > > >      */
> > > > > > }
> > > > > >
> > > > > > /***** The IRQ is automatically disabled by vectoring to
> the
> > > SWI..
> > > > .
> > > > > > however, you need to make the operation atomic with
> respect to
> > > > FIQ,
> > > > > > which is NOT disabled ***/
> > > > > >
> > > > > > PUBLIC  ARM_disableFIQ?A ; interface is ARM mode
> > > > > >
> > > > > > ARM_disableFIQ?A  PROC  CODE32
> > > > > >       MRS   R0,CPSR
> > > > > >       ORR   R0,R0,#0x0040                   ; Mask just
> the
> > FIQ
> > > > > >       MSR   CPSR_c,R0
> > > > > >       BX    R14
> > > > > >
> > > > > >       ENDP
> > > > > >
> > > > > > PUBLIC  ARM_enableFIQ?A ; interface is ARM mode
> > > > > >
> > > > > > ARM_enableFIQ?A  PROC  CODE32
> > > > > >       MRS   R0,CPSR
> > > > > >       BIC   R0,R0,#0x0040                   ; Enable just
> the
> > > FIQ
> > > > > >       MSR   CPSR_c,R0
> > > > > >       BX    R14
> > > > > >
> > > > > >       ENDP
> > > > > > END
> > > > > >
> > > > > >
> > > > > > --- In lpc2000@yahoogroups.com, "Ake Hedman, eurosource"
> > > > > <akhe@b...>
> > > > > > wrote:
> > > > > > >
> > > > > > > Hi all.
> > > > > > >
> > > > > > > I am trying to enable the watchdog but the result is a
> total
> > > > hang
> > > > > of
> > > > > > the
> > > > > > > board. Not even the bootloader is possible to reach
> after
> > > the
> > > > > crash
> > > > > > and
> > > > > > > I have to reapply power with P0.14 low to get access to
> the
> > > > > > botloader
> > > > > > > again. Reset is not enough.
> > > > > > >
> > > > > > > The code to initialize the watchdog is
> > > > > > >
> > > > > > >     // initialize the watchdog timer
> > > > > > >     WDTC = 0xffffffff; //
> > > 15000000;                        //
> > > > One
> > > > > > second
> > > > > > > = 15000000
> > > > > > >     WDMOD = WDEN | WDRESET;                    //
> Activate
> > > > > watchdog
> > > > > > >     WDFEED = 0xAA; WDFEED = 0x55;
> > > > > > >
> > > > > > > I must have misunderstood the WD functionality. What am
> I
> > > doing
> > > > > > wrong?
> > > > > > > In the above code the watchdog should not trigger until
> 5
> > > > minutes
> > > > > > > elapsed so even if a vector should be wrong the code
> that
> > > follow
> > > > > > should
> > > > > > > run for a while but as soon as I write to the WDMOD
> register
> > > I
> > > > > get a
> > > > > > hang.
> > > > > > >
> > > > > > > /Ake
> > > > > > >
> > > > > > > --
> > > > > > >  ---
> > > > > > > Ake Hedman (YAP - Yet Another Programmer)
> > > > > > > eurosource, Brattbergavägen 17, 820 50 LOS, Sweden
> > > > > > > Phone: (46) 657 413430 Cellular: (46) 73 84 84 102
> > > > > > > Company home: http://www.eurosource.se     
> > > > > > > Kryddor/Te/Kaffe: http://www.brattberg.com
> > > > > > > Personal homepage: http://www.eurosource.se/akhe
> > > > > > > Automated home: http://www.vscp.org
> > > > > > >
> > > > > >
> > > > >
> > > >
> > >
> >
>
>
>
>
>
>
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Ake Hedman (YAP - Yet Another Programmer)
eurosource, Brattbergavägen 17, 820 50 LOS, Sweden
Phone: (46) 657 413430 Cellular: (46) 73 84 84 102
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Automated home: http://www.vscp.org



[Non-text portions of this message have been removed]

Re: [lpc2000] Re: Problem with watchdog

2005-12-10 by Martin Maurer

Why Karma ? Use Paypal... :-)

Regards,

        Martin
Show quoted textHide quoted text
----- Original Message ----- 
From: "Ake Hedman, eurosource" <akhe@...>
To: <lpc2000@yahoogroups.com>
Sent: Saturday, December 10, 2005 2:22 PM
Subject: Re: [lpc2000] Re: Problem with watchdog


Hi and thankyou for this discussion.

I just want to confirm that my problems also go away when I turn of
IRQ's while feeding the dog. I have just tested it on a minimalistic
sample where I only have I2C and UART interrupts and where the problem
starts as soon as I add the I2C code.

I will try this on my real application and report back.

You are all worth a beer on me tonight  (if I only could reach you...).
Lets hope that Karma things works... :-)

/Ake

brendanmurphy37 wrote:

>
> Ken,
>
> Thanks for the reference to the previous discussion on this: it's
> exactly what I was looking for (confirmation/proof that there is
> indeed a problem).
>
> By the way, I think you may have misunderstood my comment on the
> interrupt issue. No need to explain where you're coming from: far
> from suggesting you change, I'd strongly advise keeping what you
> have, if it works and causes no problems. I've seen too many cases
> of (inexperienced) engineers tweaking something that works to "make
> it more efficient", only to see it explode in people's faces further
> down the line. As you point out, there's nothing better then the
> knowledge of maybe tens or hundreds of thousands of units in the
> field to focus the mind on reliability as THE primary consideration.
>
> It was more for the benefit of others who may be reading to point
> out there are much simpler ways of working around the quirks of ARM
> interrupts (which also give 100% reliability). Personally, I find
> this forum very useful, particularly in the mix of people
> contributing, from hobbyists to professionals, each bringing a
> particular perspective.
>
> One thing I've learnt is that there is almost never one correct
> solution to a problem. In fact, if you can't think of two or three
> solutions to a particular problem, you probably don't understand it
> well enough in the first place.
>
> My own lesson from this is that I should really have searched the
> message archive for watchdog issues before starting.
>
> I think it's a big help too to have Philips actively monitor this
> forum: I've no doubt they will react positively to this and other
> issues, and provide ammended or new documantation to describe the
> various issues with the parts.
>
> Brendan
>
>
> --- In lpc2000@yahoogroups.com, "Ken Wada" <kwada@a...> wrote:
> >
> > ok...
> > I can surely tell you this...
> > I had the Watchdog working perfectly, until I started adding
> interrupt
> > support, (mainly device drivers for the UART). After days of
> pulling
> > my hair out, and interpreting the UM for the LPC2214 as a lawyer
> would
> > do; it occured to me that the UM says 'feed 0x55 then 0xAA' It
> made
> > absolutely no mentioned about what may happen if the process got
> > preempted by an interrupt...
> >
> > Then alas; when I installed my 1st interrupt service routine; all
> > worked fine, for a few hours, and sometimes for a couple of days...
> >
> > Then my clients started complaining about 'these spurious reset
> > events'. They demanded that I fix the problem right away.
> >
> > SO...
> > I came to this forum: AND I saw this:
> > message #5470 ---> Please also read all the threads that spawned
> from
> > this message.
> >
> > Quickly, I wrappered the WDOG pet thing with my over-engineered
> SWI
> > service...(to keep any chance of those spurious interrupts thing
> from
> > happening)
> >
> > AND...
> > It has been working fine now with no glitches for about 9 months
> now.
> >
> > As a side note: from what I can see, you my be able to disable and
> > enable interrupts from the main body of your code by writing to
> the
> > CPSR...
> >
> > The big problem I have with this is that when you execute the MSR
> > instruction...the ARM architecture manual clearly states that
> there
> > may be a chance of the CPSR contents being copied into the
> interrupt
> > service CPSR_shadow with both the IRQ and FIQ bits disabled.
> >
> > You know...the probability of this type of occurence happening, in
> a
> > real system, is practically nil.
> >
> > Therefore, I decided to use the more ioctl() style of interfacing
> to
> > the device drivers using the SWI mechanism... and letting the ARM
> > pipeline and state machine sort out all the details... in terms of
> > queueing and such.
> >
> > The counter-side to my over-engineered approach is that it
> requires a
> > bit more code, and is implemented more like a immutable IOCTL()
> device
> > driver.
> >
> > The flipside to this argument, is that the IOCTL() SWI protected
> thing
> > is pretty much guaranteed to work...
> >
> > Yes, I know that what I am doing is not elegant, and perhaps a bit
> > over-engineered and maybe, in the long run unnecessary....
> >
> > But, I have been bitten too many times with issues such as this;
> > thereforem my cautious approach.
> >
> > So...you are quite correct Brendan; there really is nothing
> > specifically staing the fact that you need to stuff those two WDT
> > values back-to-back in the Philips UM.
> >
> > However, this appears to not be a new issue within this forum. In
> > fact, this is how I found out that this is an issue to begin with.
> >
> > Through this forum!!! There appears to be many other 'real world'
> > users out there that have had exactly the same experience as I
> have on
> > regards to this issue.
> >
> > Again...about the interrupts...basically I am coding all my
> protected
> > stuff using the well-known IOCTL() model wrappered within an SWI
> > interface...Instead of 'trying' different things...There was
> enough
> > stated in the ARM reference manual, and the Philips UM that got me
> > really paranoid about the whole thing....> so...> I decided that
> > caution was the best approach, and took the more circuitous...but
> > guarranteed to work approach for affecting the driver interface to
> an
> > ISR.
> >
> > By the way; if you look at the Philips interrupt-driven UART ISR,
> > (here in this forum, under files); they took exactly the same
> approach
> > in interfacing the main thread with the UART variables....They
> > protected it using an SWI wrapper!!!
> >
> > If it is good enough for Philips...I guess it probably is good
> enough
> > for me
> >
> > Besides; I already understand and know the IOCTL()/SWI model; this
> > approach to device drivers is well established and well known.
> >
> > My 1st exposure to this model came from analyzing all of that
> Borland
> > MSDOS code that ran on those old x86 machines!
> >
> > Ken Wada
> >
> > --- In lpc2000@yahoogroups.com, "brendanmurphy37"
> <brendan.murphy@i...
> > > wrote:
> > >
> > >
> > > Ken,
> > >
> > > I'm still curous about your statement "the processor expects
> > > a WRITE(0xAA) on the very next cycle". Where is this documented?
> It
> > > may be true, but if so, I'd say it contradicts the quote I took
> from
> > > the User Manual (for the LPC213x parts). Or am I misreading what
> it
> > > says?
> > >
> > > It's a fairly important point: if the feed has to be done in two
> > > adjacent CPU cycles, you're forced to use assembler apart from
> > > anything else, in order to do the back-to-back write reliably
> (I've
> > > checked the assembler o/p from our own code, and it does, but
> you
> > > can't rely on this: all you need is to change the revision of
> the
> > > compiler or have a new optimsaition setting and thinmgs can fall
> > > apart).
> > >
> > > On the other point: you're quite right - there's plenty
> of "gotchas"
> > > with ARM interrupts. It's been a while since I looked at this,
> but I
> > > seem to recall spending at least a few days armed with a stack
> of
> > > ARM books/manuals etc. (if you'll forgive the pun) to get our
> > > interrupt handling code to a state we were happy with it. Funny
> how
> > > you forget such things... I think what prompted my question was
> the
> > > implication that you somehow couldn't set both bits at the same
> > > time. As the other response on this points out, you can of
> course,
> > > and it works, but maybe not in quite the way you'd expect.....
> > >
> > > I'd apreciate an answer on the watchdog issue though, as it's
> very
> > > much a live issue with us at the moment.
> > >
> > > Regards
> > > Brendan
> > >
> > >
> > > --- In lpc2000@yahoogroups.com, "Ken Wada" <kwada@a...> wrote:
> > > >
> > > > --- In lpc2000@yahoogroups.com, "brendanmurphy37"
> > > <brendan.murphy@i...
> > > > > wrote:
> > > > >
> > > > >
> > > > > Ken,
> > > > >
> > > > > Can you explain why you think there's a problem with an
> > > interrupt
> > > > > between the two writes?
> > > > >
> > > > > According to the User Manual: "Once 0xAA is written to
> > > > > the WDFEED register the next operation in the Watchdog
> register
> > > > space
> > > > > should be a WRITE (0x55) to the WDFFED register otherwise
> the
> > > > > watchdog is triggered."
> > > > >
> > > > > I take this to mean that the next write to the WDFEED
> register
> > > has
> > > > to
> > > > > be 0x55 following the 0xaa: why should it matter if this is
> one
> > > > cycle
> > > > > on, or 1000 cycles on (e.g. to take account of any
> interrupt)?
> > > I'm
> > > > > assuming here that the interrupt itself doesn't go near the
> > > > watchdog.
> > > > It makes a bit difference! If you WRITE (0x55), the processor
> > > expects
> > > > a WRITE(0xAA) on  the very next cycle. If this is done outside
> an
> > > > interrupt context, the interrupt service routine will pretty
> much
> > > > guarantee that this condition is violated!
> > > >
> > > > >
> > > > > Also, for disabling interrupts, why not just disable IRQ and
> FIQ
> > > in
> > > > > the same write to the CPSR? Is there some problem with this?
> > > > Yep...huge problem. Actually, you will see this type of
> problem
> > > with
> > > > many processors/especially DSP's with fully pipelined
> > > architecture.
> > > > The Philips User manual calls this the spurious interrupt
> problem.
> > > > Actually, Philips basically took their cautionary note
> directly
> > > from
> > > > the ARM users guide.
> > > >
> > > > Gone are the good-old days of doing something like EA=0, as
> per
> > > 8051..
> > > > .these pipelined architectures are a bit different when it
> comes
> > > to
> > > > instruction processing.
> > > >
> > > > Fortunately, all of these modern architectures give you a way
> to
> > > do
> > > > these types of operations, (albeit with a bit more effort),
> via
> > > some
> > > > software interrupt (SWI) instruction.
> > > >
> > > > My 1st encounter with this was with the Intel 80386 chip. This
> > > chip
> > > > had an instruction pipeline, and I had to use the int86() SWI
> > > command
> > > > in order to properly code up the atomic sections.
> > > >
> > > > Ken Wada
> > > > >
> > > > > regards
> > > > > Brendan
> > > > >
> > > > >
> > > > > --- In lpc2000@yahoogroups.com, "Ken Wada" <kwada@a...>
> wrote:
> > > > > >
> > > > > > Basically, your method works fine...
> > > > > > UNTIL: you start adding interrupt service routines!
> > > > > >
> > > > > > This is why:
> > > > > > void WDOG_pet()
> > > > > > {
> > > > > > WDFEED = 0xAA;
> > > > > > /*             Interrupt occurs here...> dog will NOT pet
> > > > > properly!!!
> > > > > > ***/
> > > > > > WDFEED = 0x55;
> > > > > > }
> > > > > >
> > > > > > /**** example uses Keil compiler directives ***/
> > > > > > /********** The following is what I wound up doing, (gotta
> > > avoid
> > > > > that
> > > > > > spurious interrupt issue with the ARM also!!! ***/
> > > > > >
> > > > > > /**** The actual interface that everybody uses ***/
> > > > > > void WDOG_pet (void)
> > > > > > {
> > > > > >     SYSSWI_service (12,0,0,0);
> > > > > > }
> > > > > >
> > > > > > /***** How the SYSSWI_service works, (based on SWI) ***/
> > > > > > unsigned SYSSWI_service (SYSSWI opcode, int id, void
> *pObj,
> > > > > unsigned
> > > > > > _user1) __swi(12)
> > > > > > {
> > > > > >     switch (opcode)
> > > > > >     {
> > > > > >       case SYSSWI_WDOGPET:
> > > > > >         SYSSWI_watchDogPet ();
> > > > > >         break;
> > > > > >       ...
> > > > > >     }
> > > > > >     return (0);
> > > > > > }
> > > > > >
> > > > > > /***** How the SYSSWI_watchDogPet () works ***/
> > > > > > static void SYSSWI_watchDogPet (void)
> > > > > > {
> > > > > >     ARM_disableFIQ ();                /* make sure FIQ is
> > > > > disabled
> > > > > >      */
> > > > > >     WDFEED  = 0xAA;
> > > > > >     WDFEED  = 0x55;
> > > > > >     ARM_enableFIQ ();                 /* re-enable the
> > > > > FIQ
> > > > > >      */
> > > > > > }
> > > > > >
> > > > > > /***** The IRQ is automatically disabled by vectoring to
> the
> > > SWI..
> > > > .
> > > > > > however, you need to make the operation atomic with
> respect to
> > > > FIQ,
> > > > > > which is NOT disabled ***/
> > > > > >
> > > > > > PUBLIC  ARM_disableFIQ?A ; interface is ARM mode
> > > > > >
> > > > > > ARM_disableFIQ?A  PROC  CODE32
> > > > > >       MRS   R0,CPSR
> > > > > >       ORR   R0,R0,#0x0040                   ; Mask just
> the
> > FIQ
> > > > > >       MSR   CPSR_c,R0
> > > > > >       BX    R14
> > > > > >
> > > > > >       ENDP
> > > > > >
> > > > > > PUBLIC  ARM_enableFIQ?A ; interface is ARM mode
> > > > > >
> > > > > > ARM_enableFIQ?A  PROC  CODE32
> > > > > >       MRS   R0,CPSR
> > > > > >       BIC   R0,R0,#0x0040                   ; Enable just
> the
> > > FIQ
> > > > > >       MSR   CPSR_c,R0
> > > > > >       BX    R14
> > > > > >
> > > > > >       ENDP
> > > > > > END
> > > > > >
> > > > > >
> > > > > > --- In lpc2000@yahoogroups.com, "Ake Hedman, eurosource"
> > > > > <akhe@b...>
> > > > > > wrote:
> > > > > > >
> > > > > > > Hi all.
> > > > > > >
> > > > > > > I am trying to enable the watchdog but the result is a
> total
> > > > hang
> > > > > of
> > > > > > the
> > > > > > > board. Not even the bootloader is possible to reach
> after
> > > the
> > > > > crash
> > > > > > and
> > > > > > > I have to reapply power with P0.14 low to get access to
> the
> > > > > > botloader
> > > > > > > again. Reset is not enough.
> > > > > > >
> > > > > > > The code to initialize the watchdog is
> > > > > > >
> > > > > > >     // initialize the watchdog timer
> > > > > > >     WDTC = 0xffffffff; //
> > > 15000000;                        //
> > > > One
> > > > > > second
> > > > > > > = 15000000
> > > > > > >     WDMOD = WDEN | WDRESET;                    //
> Activate
> > > > > watchdog
> > > > > > >     WDFEED = 0xAA; WDFEED = 0x55;
> > > > > > >
> > > > > > > I must have misunderstood the WD functionality. What am
> I
> > > doing
> > > > > > wrong?
> > > > > > > In the above code the watchdog should not trigger until
> 5
> > > > minutes
> > > > > > > elapsed so even if a vector should be wrong the code
> that
> > > follow
> > > > > > should
> > > > > > > run for a while but as soon as I write to the WDMOD
> register
> > > I
> > > > > get a
> > > > > > hang.
> > > > > > >
> > > > > > > /Ake
> > > > > > >
> > > > > > > --
> > > > > > >  ---
> > > > > > > Ake Hedman (YAP - Yet Another Programmer)
> > > > > > > eurosource, Brattbergavägen 17, 820 50 LOS, Sweden
> > > > > > > Phone: (46) 657 413430 Cellular: (46) 73 84 84 102
> > > > > > > Company home: http://www.eurosource.se
> > > > > > > Kryddor/Te/Kaffe: http://www.brattberg.com
> > > > > > > Personal homepage: http://www.eurosource.se/akhe
> > > > > > > Automated home: http://www.vscp.org
> > > > > > >
> > > > > >
> > > > >
> > > >
> > >
> >
>
>
>
>
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-- 
 ---
Ake Hedman (YAP - Yet Another Programmer)
eurosource, Brattbergavägen 17, 820 50 LOS, Sweden
Phone: (46) 657 413430 Cellular: (46) 73 84 84 102
Company home: http://www.eurosource.se
Kryddor/Te/Kaffe: http://www.brattberg.com
Personal homepage: http://www.eurosource.se/akhe
Automated home: http://www.vscp.org



[Non-text portions of this message have been removed]





Yahoo! Groups Links

Re: [lpc2000] Re: Problem with watchdog

2005-12-10 by Ake Hedman, eurosource

;-)

/Ake

Martin Maurer wrote:

> Why Karma ? Use Paypal... :-)
>
> Regards,
>
>         Martin
>
> ----- Original Message -----
> From: "Ake Hedman, eurosource" <akhe@...>
> To: <lpc2000@yahoogroups.com>
> Sent: Saturday, December 10, 2005 2:22 PM
> Subject: Re: [lpc2000] Re: Problem with watchdog
>
>
> Hi and thankyou for this discussion.
>
> I just want to confirm that my problems also go away when I turn of
> IRQ's while feeding the dog. I have just tested it on a minimalistic
> sample where I only have I2C and UART interrupts and where the problem
> starts as soon as I add the I2C code.
>
> I will try this on my real application and report back.
>
> You are all worth a beer on me tonight  (if I only could reach you...).
> Lets hope that Karma things works... :-)
>
> /Ake
>
> brendanmurphy37 wrote:
>
> >
> > Ken,
> >
> > Thanks for the reference to the previous discussion on this: it's
> > exactly what I was looking for (confirmation/proof that there is
> > indeed a problem).
> >
> > By the way, I think you may have misunderstood my comment on the
> > interrupt issue. No need to explain where you're coming from: far
> > from suggesting you change, I'd strongly advise keeping what you
> > have, if it works and causes no problems. I've seen too many cases
> > of (inexperienced) engineers tweaking something that works to "make
> > it more efficient", only to see it explode in people's faces further
> > down the line. As you point out, there's nothing better then the
> > knowledge of maybe tens or hundreds of thousands of units in the
> > field to focus the mind on reliability as THE primary consideration.
> >
> > It was more for the benefit of others who may be reading to point
> > out there are much simpler ways of working around the quirks of ARM
> > interrupts (which also give 100% reliability). Personally, I find
> > this forum very useful, particularly in the mix of people
> > contributing, from hobbyists to professionals, each bringing a
> > particular perspective.
> >
> > One thing I've learnt is that there is almost never one correct
> > solution to a problem. In fact, if you can't think of two or three
> > solutions to a particular problem, you probably don't understand it
> > well enough in the first place.
> >
> > My own lesson from this is that I should really have searched the
> > message archive for watchdog issues before starting.
> >
> > I think it's a big help too to have Philips actively monitor this
> > forum: I've no doubt they will react positively to this and other
> > issues, and provide ammended or new documantation to describe the
> > various issues with the parts.
> >
> > Brendan
> >
> >
> > --- In lpc2000@yahoogroups.com, "Ken Wada" <kwada@a...> wrote:
> > >
> > > ok...
> > > I can surely tell you this...
> > > I had the Watchdog working perfectly, until I started adding
> > interrupt
> > > support, (mainly device drivers for the UART). After days of
> > pulling
> > > my hair out, and interpreting the UM for the LPC2214 as a lawyer
> > would
> > > do; it occured to me that the UM says 'feed 0x55 then 0xAA' It
> > made
> > > absolutely no mentioned about what may happen if the process got
> > > preempted by an interrupt...
> > >
> > > Then alas; when I installed my 1st interrupt service routine; all
> > > worked fine, for a few hours, and sometimes for a couple of days...
> > >
> > > Then my clients started complaining about 'these spurious reset
> > > events'. They demanded that I fix the problem right away.
> > >
> > > SO...
> > > I came to this forum: AND I saw this:
> > > message #5470 ---> Please also read all the threads that spawned
> > from
> > > this message.
> > >
> > > Quickly, I wrappered the WDOG pet thing with my over-engineered
> > SWI
> > > service...(to keep any chance of those spurious interrupts thing
> > from
> > > happening)
> > >
> > > AND...
> > > It has been working fine now with no glitches for about 9 months
> > now.
> > >
> > > As a side note: from what I can see, you my be able to disable and
> > > enable interrupts from the main body of your code by writing to
> > the
> > > CPSR...
> > >
> > > The big problem I have with this is that when you execute the MSR
> > > instruction...the ARM architecture manual clearly states that
> > there
> > > may be a chance of the CPSR contents being copied into the
> > interrupt
> > > service CPSR_shadow with both the IRQ and FIQ bits disabled.
> > >
> > > You know...the probability of this type of occurence happening, in
> > a
> > > real system, is practically nil.
> > >
> > > Therefore, I decided to use the more ioctl() style of interfacing
> > to
> > > the device drivers using the SWI mechanism... and letting the ARM
> > > pipeline and state machine sort out all the details... in terms of
> > > queueing and such.
> > >
> > > The counter-side to my over-engineered approach is that it
> > requires a
> > > bit more code, and is implemented more like a immutable IOCTL()
> > device
> > > driver.
> > >
> > > The flipside to this argument, is that the IOCTL() SWI protected
> > thing
> > > is pretty much guaranteed to work...
> > >
> > > Yes, I know that what I am doing is not elegant, and perhaps a bit
> > > over-engineered and maybe, in the long run unnecessary....
> > >
> > > But, I have been bitten too many times with issues such as this;
> > > thereforem my cautious approach.
> > >
> > > So...you are quite correct Brendan; there really is nothing
> > > specifically staing the fact that you need to stuff those two WDT
> > > values back-to-back in the Philips UM.
> > >
> > > However, this appears to not be a new issue within this forum. In
> > > fact, this is how I found out that this is an issue to begin with.
> > >
> > > Through this forum!!! There appears to be many other 'real world'
> > > users out there that have had exactly the same experience as I
> > have on
> > > regards to this issue.
> > >
> > > Again...about the interrupts...basically I am coding all my
> > protected
> > > stuff using the well-known IOCTL() model wrappered within an SWI
> > > interface...Instead of 'trying' different things...There was
> > enough
> > > stated in the ARM reference manual, and the Philips UM that got me
> > > really paranoid about the whole thing....> so...> I decided that
> > > caution was the best approach, and took the more circuitous...but
> > > guarranteed to work approach for affecting the driver interface to
> > an
> > > ISR.
> > >
> > > By the way; if you look at the Philips interrupt-driven UART ISR,
> > > (here in this forum, under files); they took exactly the same
> > approach
> > > in interfacing the main thread with the UART variables....They
> > > protected it using an SWI wrapper!!!
> > >
> > > If it is good enough for Philips...I guess it probably is good
> > enough
> > > for me
> > >
> > > Besides; I already understand and know the IOCTL()/SWI model; this
> > > approach to device drivers is well established and well known.
> > >
> > > My 1st exposure to this model came from analyzing all of that
> > Borland
> > > MSDOS code that ran on those old x86 machines!
> > >
> > > Ken Wada
> > >
> > > --- In lpc2000@yahoogroups.com, "brendanmurphy37"
> > <brendan.murphy@i...
> > > > wrote:
> > > >
> > > >
> > > > Ken,
> > > >
> > > > I'm still curous about your statement "the processor expects
> > > > a WRITE(0xAA) on the very next cycle". Where is this documented?
> > It
> > > > may be true, but if so, I'd say it contradicts the quote I took
> > from
> > > > the User Manual (for the LPC213x parts). Or am I misreading what
> > it
> > > > says?
> > > >
> > > > It's a fairly important point: if the feed has to be done in two
> > > > adjacent CPU cycles, you're forced to use assembler apart from
> > > > anything else, in order to do the back-to-back write reliably
> > (I've
> > > > checked the assembler o/p from our own code, and it does, but
> > you
> > > > can't rely on this: all you need is to change the revision of
> > the
> > > > compiler or have a new optimsaition setting and thinmgs can fall
> > > > apart).
> > > >
> > > > On the other point: you're quite right - there's plenty
> > of "gotchas"
> > > > with ARM interrupts. It's been a while since I looked at this,
> > but I
> > > > seem to recall spending at least a few days armed with a stack
> > of
> > > > ARM books/manuals etc. (if you'll forgive the pun) to get our
> > > > interrupt handling code to a state we were happy with it. Funny
> > how
> > > > you forget such things... I think what prompted my question was
> > the
> > > > implication that you somehow couldn't set both bits at the same
> > > > time. As the other response on this points out, you can of
> > course,
> > > > and it works, but maybe not in quite the way you'd expect.....
> > > >
> > > > I'd apreciate an answer on the watchdog issue though, as it's
> > very
> > > > much a live issue with us at the moment.
> > > >
> > > > Regards
> > > > Brendan
> > > >
> > > >
> > > > --- In lpc2000@yahoogroups.com, "Ken Wada" <kwada@a...> wrote:
> > > > >
> > > > > --- In lpc2000@yahoogroups.com, "brendanmurphy37"
> > > > <brendan.murphy@i...
> > > > > > wrote:
> > > > > >
> > > > > >
> > > > > > Ken,
> > > > > >
> > > > > > Can you explain why you think there's a problem with an
> > > > interrupt
> > > > > > between the two writes?
> > > > > >
> > > > > > According to the User Manual: "Once 0xAA is written to
> > > > > > the WDFEED register the next operation in the Watchdog
> > register
> > > > > space
> > > > > > should be a WRITE (0x55) to the WDFFED register otherwise
> > the
> > > > > > watchdog is triggered."
> > > > > >
> > > > > > I take this to mean that the next write to the WDFEED
> > register
> > > > has
> > > > > to
> > > > > > be 0x55 following the 0xaa: why should it matter if this is
> > one
> > > > > cycle
> > > > > > on, or 1000 cycles on (e.g. to take account of any
> > interrupt)?
> > > > I'm
> > > > > > assuming here that the interrupt itself doesn't go near the
> > > > > watchdog.
> > > > > It makes a bit difference! If you WRITE (0x55), the processor
> > > > expects
> > > > > a WRITE(0xAA) on  the very next cycle. If this is done outside
> > an
> > > > > interrupt context, the interrupt service routine will pretty
> > much
> > > > > guarantee that this condition is violated!
> > > > >
> > > > > >
> > > > > > Also, for disabling interrupts, why not just disable IRQ and
> > FIQ
> > > > in
> > > > > > the same write to the CPSR? Is there some problem with this?
> > > > > Yep...huge problem. Actually, you will see this type of
> > problem
> > > > with
> > > > > many processors/especially DSP's with fully pipelined
> > > > architecture.
> > > > > The Philips User manual calls this the spurious interrupt
> > problem.
> > > > > Actually, Philips basically took their cautionary note
> > directly
> > > > from
> > > > > the ARM users guide.
> > > > >
> > > > > Gone are the good-old days of doing something like EA=0, as
> > per
> > > > 8051..
> > > > > .these pipelined architectures are a bit different when it
> > comes
> > > > to
> > > > > instruction processing.
> > > > >
> > > > > Fortunately, all of these modern architectures give you a way
> > to
> > > > do
> > > > > these types of operations, (albeit with a bit more effort),
> > via
> > > > some
> > > > > software interrupt (SWI) instruction.
> > > > >
> > > > > My 1st encounter with this was with the Intel 80386 chip. This
> > > > chip
> > > > > had an instruction pipeline, and I had to use the int86() SWI
> > > > command
> > > > > in order to properly code up the atomic sections.
> > > > >
> > > > > Ken Wada
> > > > > >
> > > > > > regards
> > > > > > Brendan
> > > > > >
> > > > > >
> > > > > > --- In lpc2000@yahoogroups.com, "Ken Wada" <kwada@a...>
> > wrote:
> > > > > > >
> > > > > > > Basically, your method works fine...
> > > > > > > UNTIL: you start adding interrupt service routines!
> > > > > > >
> > > > > > > This is why:
> > > > > > > void WDOG_pet()
> > > > > > > {
> > > > > > > WDFEED = 0xAA;
> > > > > > > /*             Interrupt occurs here...> dog will NOT pet
> > > > > > properly!!!
> > > > > > > ***/
> > > > > > > WDFEED = 0x55;
> > > > > > > }
> > > > > > >
> > > > > > > /**** example uses Keil compiler directives ***/
> > > > > > > /********** The following is what I wound up doing, (gotta
> > > > avoid
> > > > > > that
> > > > > > > spurious interrupt issue with the ARM also!!! ***/
> > > > > > >
> > > > > > > /**** The actual interface that everybody uses ***/
> > > > > > > void WDOG_pet (void)
> > > > > > > {
> > > > > > >     SYSSWI_service (12,0,0,0);
> > > > > > > }
> > > > > > >
> > > > > > > /***** How the SYSSWI_service works, (based on SWI) ***/
> > > > > > > unsigned SYSSWI_service (SYSSWI opcode, int id, void
> > *pObj,
> > > > > > unsigned
> > > > > > > _user1) __swi(12)
> > > > > > > {
> > > > > > >     switch (opcode)
> > > > > > >     {
> > > > > > >       case SYSSWI_WDOGPET:
> > > > > > >         SYSSWI_watchDogPet ();
> > > > > > >         break;
> > > > > > >       ...
> > > > > > >     }
> > > > > > >     return (0);
> > > > > > > }
> > > > > > >
> > > > > > > /***** How the SYSSWI_watchDogPet () works ***/
> > > > > > > static void SYSSWI_watchDogPet (void)
> > > > > > > {
> > > > > > >     ARM_disableFIQ ();                /* make sure FIQ is
> > > > > > disabled
> > > > > > >      */
> > > > > > >     WDFEED  = 0xAA;
> > > > > > >     WDFEED  = 0x55;
> > > > > > >     ARM_enableFIQ ();                 /* re-enable the
> > > > > > FIQ
> > > > > > >      */
> > > > > > > }
> > > > > > >
> > > > > > > /***** The IRQ is automatically disabled by vectoring to
> > the
> > > > SWI..
> > > > > .
> > > > > > > however, you need to make the operation atomic with
> > respect to
> > > > > FIQ,
> > > > > > > which is NOT disabled ***/
> > > > > > >
> > > > > > > PUBLIC  ARM_disableFIQ?A ; interface is ARM mode
> > > > > > >
> > > > > > > ARM_disableFIQ?A  PROC  CODE32
> > > > > > >       MRS   R0,CPSR
> > > > > > >       ORR   R0,R0,#0x0040                   ; Mask just
> > the
> > > FIQ
> > > > > > >       MSR   CPSR_c,R0
> > > > > > >       BX    R14
> > > > > > >
> > > > > > >       ENDP
> > > > > > >
> > > > > > > PUBLIC  ARM_enableFIQ?A ; interface is ARM mode
> > > > > > >
> > > > > > > ARM_enableFIQ?A  PROC  CODE32
> > > > > > >       MRS   R0,CPSR
> > > > > > >       BIC   R0,R0,#0x0040                   ; Enable just
> > the
> > > > FIQ
> > > > > > >       MSR   CPSR_c,R0
> > > > > > >       BX    R14
> > > > > > >
> > > > > > >       ENDP
> > > > > > > END
> > > > > > >
> > > > > > >
> > > > > > > --- In lpc2000@yahoogroups.com, "Ake Hedman, eurosource"
> > > > > > <akhe@b...>
> > > > > > > wrote:
> > > > > > > >
> > > > > > > > Hi all.
> > > > > > > >
> > > > > > > > I am trying to enable the watchdog but the result is a
> > total
> > > > > hang
> > > > > > of
> > > > > > > the
> > > > > > > > board. Not even the bootloader is possible to reach
> > after
> > > > the
> > > > > > crash
> > > > > > > and
> > > > > > > > I have to reapply power with P0.14 low to get access to
> > the
> > > > > > > botloader
> > > > > > > > again. Reset is not enough.
> > > > > > > >
> > > > > > > > The code to initialize the watchdog is
> > > > > > > >
> > > > > > > >     // initialize the watchdog timer
> > > > > > > >     WDTC = 0xffffffff; //
> > > > 15000000;                        //
> > > > > One
> > > > > > > second
> > > > > > > > = 15000000
> > > > > > > >     WDMOD = WDEN | WDRESET;                    //
> > Activate
> > > > > > watchdog
> > > > > > > >     WDFEED = 0xAA; WDFEED = 0x55;
> > > > > > > >
> > > > > > > > I must have misunderstood the WD functionality. What am
> > I
> > > > doing
> > > > > > > wrong?
> > > > > > > > In the above code the watchdog should not trigger until
> > 5
> > > > > minutes
> > > > > > > > elapsed so even if a vector should be wrong the code
> > that
> > > > follow
> > > > > > > should
> > > > > > > > run for a while but as soon as I write to the WDMOD
> > register
> > > > I
> > > > > > get a
> > > > > > > hang.
> > > > > > > >
> > > > > > > > /Ake
> > > > > > > >
> > > > > > > > --
> > > > > > > >  ---
> > > > > > > > Ake Hedman (YAP - Yet Another Programmer)
> > > > > > > > eurosource, Brattbergavägen 17, 820 50 LOS, Sweden
> > > > > > > > Phone: (46) 657 413430 Cellular: (46) 73 84 84 102
> > > > > > > > Company home: http://www.eurosource.se
> > > > > > > > Kryddor/Te/Kaffe: http://www.brattberg.com
> > > > > > > > Personal homepage: http://www.eurosource.se/akhe
> > > > > > > > Automated home: http://www.vscp.org
> > > > > > > >
> > > > > > >
> > > > > >
> > > > >
> > > >
> > >
> >
> >
> >
> >
> >
> >
> > SPONSORED LINKS
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> > 
> <http://groups.yahoo.com/gads?t=ms&k=Microprocessor&w1=Microprocessor&w2=Microcontrollers&w3=Pic+microcontrollers&w4=8051+microprocessor&c=4&s=93&.sig=tsVC-J9hJ5qyXg0WPR0l6g 
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> Ake Hedman (YAP - Yet Another Programmer)
> eurosource, Brattbergavägen 17, 820 50 LOS, Sweden
> Phone: (46) 657 413430 Cellular: (46) 73 84 84 102
> Company home: http://www.eurosource.se
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-- 
 ---
Ake Hedman (YAP - Yet Another Programmer)
eurosource, Brattbergavägen 17, 820 50 LOS, Sweden
Phone: (46) 657 413430 Cellular: (46) 73 84 84 102
Company home: http://www.eurosource.se      
Kryddor/Te/Kaffe: http://www.brattberg.com
Personal homepage: http://www.eurosource.se/akhe
Automated home: http://www.vscp.org



[Non-text portions of this message have been removed]

Re: [lpc2000] Re: Problem with watchdog

2005-12-10 by Ake Hedman, eurosource

OK Guys,

I can confirm that the WD problem is solved in my case. Thanks a lot 
all!  (Description of solution below.)

I think this definitely should be mentioned in the err data sheets for 
the affected processors (or clearly in the UM)  as the resulting 
symptoms are such that the problem is very hard to debug..

Cheers
/Ake


How I solved it:

I have replaced all dog-feeds with

        mycpsr = disableIRQ();
        WDFEED = 0xAA; WDFEED = 0x55;
        restoreIRQ( mycpsr );

where disableIRQ and restoreIRQ is from R O Software

/******************************************************************************
 *
 * $RCSfile: armVIC.c,v $
 * $Revision: 1.1 $
 *
 * This module provides the interface routines for setting up and
 * controlling the various interrupt modes present on the ARM processor.
 * Copyright 2004, R O SoftWare
 * No guarantees, warrantees, or promises, implied or otherwise.
 * May be used for hobby or commercial purposes provided copyright
 * notice remains intact.
 *
 *****************************************************************************/
#include "types.h"
#include "armVIC.h"

#define IRQ_MASK 0x00000080
#define FIQ_MASK 0x00000040
#define INT_MASK (IRQ_MASK | FIQ_MASK)

static inline unsigned __get_cpsr(void)
{
  unsigned long retval;
  asm volatile (" mrs  %0, cpsr" : "=r" (retval) : /* no inputs */  );
  return retval;
}

static inline void __set_cpsr(unsigned val)
{
  asm volatile (" msr  cpsr, %0" : /* no outputs */ : "r" (val)  );
}

unsigned disableIRQ(void)
{
  unsigned _cpsr;

  _cpsr = __get_cpsr();
  __set_cpsr(_cpsr | IRQ_MASK);
  return _cpsr;
}

unsigned restoreIRQ(unsigned oldCPSR)
{
  unsigned _cpsr;

  _cpsr = __get_cpsr();
  __set_cpsr((_cpsr & ~IRQ_MASK) | (oldCPSR & IRQ_MASK));
  return _cpsr;
}

unsigned enableIRQ(void)
{
  unsigned _cpsr;

  _cpsr = __get_cpsr();
  __set_cpsr(_cpsr & ~IRQ_MASK);
  return _cpsr;
}

unsigned disableFIQ(void)
{
  unsigned _cpsr;

  _cpsr = __get_cpsr();
  __set_cpsr(_cpsr | FIQ_MASK);
  return _cpsr;
}

unsigned restoreFIQ(unsigned oldCPSR)
{
  unsigned _cpsr;

  _cpsr = __get_cpsr();
  __set_cpsr((_cpsr & ~FIQ_MASK) | (oldCPSR & FIQ_MASK));
  return _cpsr;
}

unsigned enableFIQ(void)
{
  unsigned _cpsr;

  _cpsr = __get_cpsr();
  __set_cpsr(_cpsr & ~FIQ_MASK);
  return _cpsr;
}







-- 
 ---
Ake Hedman (YAP - Yet Another Programmer)
eurosource, Brattbergavägen 17, 820 50 LOS, Sweden
Phone: (46) 657 413430 Cellular: (46) 73 84 84 102
Company home: http://www.eurosource.se      
Kryddor/Te/Kaffe: http://www.brattberg.com
Personal homepage: http://www.eurosource.se/akhe
Automated home: http://www.vscp.org

Re: [lpc2000] Re: Problem with watchdog

2005-12-11 by Tom Walsh

Ake Hedman, eurosource wrote:

>OK Guys,
>
>I can confirm that the WD problem is solved in my case. Thanks a lot 
>all!  (Description of solution below.)
>
>I think this definitely should be mentioned in the err data sheets for 
>the affected processors (or clearly in the UM)  as the resulting 
>symptoms are such that the problem is very hard to debug..
>
>Cheers
>/Ake
>
>
>How I solved it:
>
>I have replaced all dog-feeds with
>
>        mycpsr = disableIRQ();
>        WDFEED = 0xAA; WDFEED = 0x55;
>        restoreIRQ( mycpsr );
>
>where disableIRQ and restoreIRQ is from R O Software
>
>  
>

I've been following this thread with interest as I expected to use the 
watchdog in my application.  The old design used a MAX690 where you 
would toggle the input to keep the watchdog happy.  This worked well for 
us as the foreground software would set the pin high and the interrupt 
routines would reset it low.  This ensured that both sections of the 
program were operating okay.  Foreground did non-time-critical tasks 
while the background serviced realtime critical tasks & communications 
over RS485.

I had expected to do something similar with the LPC2000 parts.  Feed the 
watchdog with 0xaa from the interrupt layer and then feed it with 0x55 
from the foreground.  It was expected that even if the watchdog received 
something like this, it would still be fine:

0xaa, 0xaa, 0xaa, 0x55, 0xaa, 0xaa, 0xaa, 0xaa, 0x55 ....


What value is a watchdog that requires you to carefully feed it, it 
sounds as if the watchdog is very fragile?  I noticed that Philips 
Applications people studiously stayed out of this thread about the 
watchdog!  I suspect that the watchdog is severly broken and they did 
not want to comment on it?


Regards,

TomW

-- 
Tom Walsh - WN3L - Embedded Systems Consultant
http://openhardware.net, http://cyberiansoftware.com
"Windows? No thanks, I have work to do..."
----------------------------------------------------

Re: [lpc2000] Re: Problem with watchdog

2005-12-11 by Ake Hedman, eurosource

Tom Walsh wrote:

>
> I've been following this thread with interest as I expected to use the
> watchdog in my application.  The old design used a MAX690 where you
> would toggle the input to keep the watchdog happy.  This worked well for
> us as the foreground software would set the pin high and the interrupt
> routines would reset it low.  This ensured that both sections of the
> program were operating okay.  Foreground did non-time-critical tasks
> while the background serviced realtime critical tasks & communications
> over RS485.
>
> I had expected to do something similar with the LPC2000 parts.  Feed the
> watchdog with 0xaa from the interrupt layer and then feed it with 0x55
> from the foreground.  It was expected that even if the watchdog received
> something like this, it would still be fine:
>
> 0xaa, 0xaa, 0xaa, 0x55, 0xaa, 0xaa, 0xaa, 0xaa, 0x55 ....
>
>
> What value is a watchdog that requires you to carefully feed it, it
> sounds as if the watchdog is very fragile?  I noticed that Philips
> Applications people studiously stayed out of this thread about the
> watchdog!  I suspect that the watchdog is severly broken and they did
> not want to comment on it?
>
>
> Regards,
>
> TomW


At least I would say that its a bit strange behavior for a watchdog. 
Anyway there is a work around and it appears to work well (at least in 
my case). I have only noticed this on the LPC2138 part so I don't know 
if the same "problem" appears on other silicon. If it is that would have 
been nice to now though.

/Ake

-- 
 ---
Ake Hedman (YAP - Yet Another Programmer)
eurosource, Brattbergavägen 17, 820 50 LOS, Sweden
Phone: (46) 657 413430 Cellular: (46) 73 84 84 102
Company home: http://www.eurosource.se      
Kryddor/Te/Kaffe: http://www.brattberg.com
Personal homepage: http://www.eurosource.se/akhe
Automated home: http://www.vscp.org

Re: [lpc2000] Re: Problem with watchdog

2005-12-11 by Robert Adsett

At 01:09 AM 12/11/05 -0500, Tom Walsh wrote:
>I've been following this thread with interest as I expected to use the
>watchdog in my application.  The old design used a MAX690 where you
>would toggle the input to keep the watchdog happy.  This worked well for
>us as the foreground software would set the pin high and the interrupt
>routines would reset it low.  This ensured that both sections of the
>program were operating okay.  Foreground did non-time-critical tasks
>while the background serviced realtime critical tasks & communications
>over RS485.
>
>I had expected to do something similar with the LPC2000 parts.  Feed the
>watchdog with 0xaa from the interrupt layer and then feed it with 0x55
>from the foreground.  It was expected that even if the watchdog received
>something like this, it would still be fine:
>
>0xaa, 0xaa, 0xaa, 0x55, 0xaa, 0xaa, 0xaa, 0xaa, 0x55 ....
>
>
>What value is a watchdog that requires you to carefully feed it, it
>sounds as if the watchdog is very fragile?


Actually, that is rather the point.  The idea is to prevent being able to 
accidentally satisfy the watchdog with writes from multiple places in the 
program.  Watchdogs are supposed to be somewhat twitchy.  Even so an 
internal watchdog doesn't usually catch events like loss of 
oscillator.  The Philips watchdog also appears to allow the trip time to be 
reprogrammed during operation which is a big weakness.

BTW this is not an unusual requirement for microcontroller based watchdogs, 
at least in my experience.

You may find (if you haven't read it already) Jack Ganssle's article on 
watchdogs interesting.  http://www.ganssle.com/watchdogs.pdf



>I noticed that Philips
>Applications people studiously stayed out of this thread about the
>watchdog!  I suspect that the watchdog is severly broken and they did
>not want to comment on it?

Actually, from these accounts the watchdog is fine.  The documentation 
needs to be updated though.  The line referring the watchdog register space 
probably needs to be updated to match the wording used for the PLLFEED 
register which explicitly refers to back to back VPB writes being 
needed.  I expect the two peripherals are using identical logic.

I wouldn't mind that period hole being fixed though, and maybe even seeing 
a minimum time between feeds enforced.

Robert

" 'Freedom' has no meaning of itself.  There are always restrictions,   be 
they legal, genetic, or physical.  If you don't believe me, try to chew a 
radio signal. "  -- Kelvin Throop, III
http://www.aeolusdevelopment.com/

Re: Problem with watchdog

2005-12-11 by derbaier

--- In lpc2000@yahoogroups.com, Tom Walsh <tom@o...> wrote:
> 
> I had expected to do something similar with the LPC2000 parts.  Feed
the 
> watchdog with 0xaa from the interrupt layer and then feed it with 0x55 
> from the foreground.  It was expected that even if the watchdog
received 
> something like this, it would still be fine:
> 
> 0xaa, 0xaa, 0xaa, 0x55, 0xaa, 0xaa, 0xaa, 0xaa, 0x55 ....
> 
> 
> What value is a watchdog that requires you to carefully feed it, it 
> sounds as if the watchdog is very fragile?  I noticed that Philips 
> Applications people studiously stayed out of this thread about the 
> watchdog!  I suspect that the watchdog is severly broken and they did 
> not want to comment on it?
> 
> 
> Regards,
> 
> TomW
> 
> -- 
> Tom Walsh - WN3L - Embedded Systems Consultant
> http://openhardware.net, http://cyberiansoftware.com
> "Windows? No thanks, I have work to do..."
> ----------------------------------------------------
>
It sounds like you have described a really robust watchdog timer!! 
It detects and stops fragile software.

It's function is NOT to make life easy for the software developer, it
is to make the system more reliable for the end user by forcing good
software and hardware design.  The watchdog kick should always be
cosecutive instructions to reduce the possibility of random events
from kicking the timer.

At least, that was the philosophy of the ASIC teams that I have worked
with.

--Dave

Re: [lpc2000] Re: Problem with watchdog

2005-12-11 by Ake Hedman, eurosource

derbaier wrote:

> --- In lpc2000@yahoogroups.com, Tom Walsh <tom@o...> wrote:
> >
> > I had expected to do something similar with the LPC2000 parts.  Feed
> the
> > watchdog with 0xaa from the interrupt layer and then feed it with 0x55
> > from the foreground.  It was expected that even if the watchdog
> received
> > something like this, it would still be fine:
> >
> > 0xaa, 0xaa, 0xaa, 0x55, 0xaa, 0xaa, 0xaa, 0xaa, 0x55 ....
> >
> >
> > What value is a watchdog that requires you to carefully feed it, it
> > sounds as if the watchdog is very fragile?  I noticed that Philips
> > Applications people studiously stayed out of this thread about the
> > watchdog!  I suspect that the watchdog is severly broken and they did
> > not want to comment on it?
> >
> >
> > Regards,
> >
> > TomW
> >
> > --
> > Tom Walsh - WN3L - Embedded Systems Consultant
> > http://openhardware.net, http://cyberiansoftware.com
> > "Windows? No thanks, I have work to do..."
> > ----------------------------------------------------
> >
> It sounds like you have described a really robust watchdog timer!!
> It detects and stops fragile software.
>
> It's function is NOT to make life easy for the software developer, it
> is to make the system more reliable for the end user by forcing good
> software and hardware design.  The watchdog kick should always be
> cosecutive instructions to reduce the possibility of random events
> from kicking the timer.
>
> At least, that was the philosophy of the ASIC teams that I have worked
> with.
>
> --Dave
>
>
The absolute majority of watchdogs, internal or external, function by 
toggling a bit  from time to time. Where in the code  you do this 
toggling is something you have to investigate for each project. The 
common point in any case is that if the program pass a certain point in 
the flow we allow the application to live for n milliseconds more. 

The 0xAA, 0x55 sequence is nothing else either. It may look safer then 
toggling a bit but false watchdog triggers have never been a problem for 
an extended time during my years as an embedded developer. The chance 
that your crashed program start to toggle a watchdog bit or write a 
0xAA, 0x55 sequence is just minimal and in that light I think Tom's 
reasoning is fully correct and would not make the watchdogs 
functionality less good. At least IMHO.

But requiring the 0xAA,0x55 sequence is acceptable to of course. The 
need to mask interrupts while doing it is not. Thats really bad.

/Ake

-- 
 ---
Ake Hedman (YAP - Yet Another Programmer)
eurosource, Brattbergavägen 17, 820 50 LOS, Sweden
Phone: (46) 657 413430 Cellular: (46) 73 84 84 102
Company home: http://www.eurosource.se      
Kryddor/Te/Kaffe: http://www.brattberg.com
Personal homepage: http://www.eurosource.se/akhe
Automated home: http://www.vscp.org

Re: [lpc2000] Re: Problem with watchdog

2005-12-11 by Robert Adsett

At 07:10 PM 12/11/05 +0100, Ake Hedman, eurosource wrote:
>The absolute majority of watchdogs, internal or external, function by
>toggling a bit  from time to time. Where in the code  you do this
>toggling is something you have to investigate for each project. The
>common point in any case is that if the program pass a certain point in
>the flow we allow the application to live for n milliseconds more.
>
>The 0xAA, 0x55 sequence is nothing else either. It may look safer then
>toggling a bit but false watchdog triggers have never been a problem for
>an extended time during my years as an embedded developer. The chance
>that your crashed program start to toggle a watchdog bit or write a
>0xAA, 0x55 sequence is just minimal and in that light I think Tom's
>reasoning is fully correct and would not make the watchdogs
>functionality less good. At least IMHO.

Umm minimal chances are what the watchdog is there to protect against.  If 
the chance isn't minimal you can make a very good case that is should be 
covered in your application code and dealt with there.


>But requiring the 0xAA,0x55 sequence is acceptable to of course. The
>need to mask interrupts while doing it is not. Thats really bad.

This is far from unusual.  To quote from the 8xc196MC user manual

"We recommend that you disable interrupts before writing to the watchdog 
register.  If an interrupt occurs between two writes, the watchdog register 
will not be cleared."

The Freescale M68HC11 family acts in the manner you suggest, while the 
ST10/C167 family from ST and Infinion use a single 'protected instruction' 
which is effectively two instructions in series to perform the 
feed.  Effectively ST/Infinion have integrated the feed and interrupt 
protection into a single instruction.  Note that the later family also 
implements Oscillator watchdogs on many of the family members.

Robert

" 'Freedom' has no meaning of itself.  There are always restrictions,   be 
they legal, genetic, or physical.  If you don't believe me, try to chew a 
radio signal. "  -- Kelvin Throop, III
http://www.aeolusdevelopment.com/

Re: Problem with watchdog

2005-12-11 by derbaier

--- In lpc2000@yahoogroups.com, "Ake Hedman, eurosource" <akhe@b...>
wrote:
>

> >
> >
> The absolute majority of watchdogs, internal or external, function by 
> toggling a bit  from time to time. Where in the code  you do this 
> toggling is something you have to investigate for each project. The 
> common point in any case is that if the program pass a certain point in 
> the flow we allow the application to live for n milliseconds more. 

True enough.  :-)

> 
> The 0xAA, 0x55 sequence is nothing else either. It may look safer then 
> toggling a bit but false watchdog triggers have never been a problem
for 
> an extended time during my years as an embedded developer. The chance 
> that your crashed program start to toggle a watchdog bit or write a 
> 0xAA, 0x55 sequence is just minimal and in that light I think Tom's 
> reasoning is fully correct and would not make the watchdogs 
> functionality less good. At least IMHO.

Minimal is NOT zero, so conservative hardware design pratices dictate
erring on the side of caution.  IMHO, that reasoning makes the
software design task easier, but makes the watchdog less reliable when
atomic kick sequences are not required.


> 
> But requiring the 0xAA,0x55 sequence is acceptable to of course. The 
> need to mask interrupts while doing it is not. Thats really bad.
> 
Bad is probably a matter of opinion?
More difficult, certainly.

The need for atomic code sequences is not all that unusual, so it is
just something that needs to be dealt with in the software design,IMHO.


-- Dave

Re: Problem with watchdog

2005-12-12 by brendanmurphy37

Robert,

Thanks for the reference to the watchdog paper - I hadn't seen it 
before, and it's certainly very good i/p to watchdog design.

I'd agree with the argument that to be really robust, you need to 
consider more than just an on-board watchdog with something giving it 
a feed now and then.

Tom: putting together a system where the background does half the 
watchdig task, and interrupts the other is a good idea in principle. 
However, it does need careful thought as to the detail: I have seen 
such a scheme fail: the watchdog needed to toggle a pin to be fed. 
The main (system) loop put the pin one way and a timer interrupt put 
it another. The problem was the system could get into a state (after 
a very heavy burst of RF noise) where the watchdog was being fed, but 
the system was effectively dead as not much else was running.

Jack Ganssle's paper gives one way out of this (a supervisory task 
monitoring the health of all other tasks). There are alternatives. 
For example, we have a watchdog message passed from one active task 
to the other (if it's in a happy state): if it reaches the watchdog 
task, the watchdog gets set (from one and only one location that's 
not in a loop). A new message is then generated by the watchdog task 
with a one second delay. In other words, for the watchdog to be fed, 
all the system's tasks/components have to be in a "happy" state, task 
scheduling, timers etc. all have to be working. It's really down to 
balance between what gives good coverage to complexity of 
implementation etc.

For what it's worth, my own view is:

- the LPC2000 watchdog is fine for an on-board watchdog (with 
corrected documentation!)

- to detect all failures, you have to go to an off-chip watchdog (or 
at least one that doesn't use ANY shared component - in particular 
the clock)

- you need to put some thought into the software to drive it: simple 
minded implementations will give better than nothing, but can be 
greatly imrpoved on

- try not to feed a watchdog from a software loop: there's a chance a 
wayword processor will end up in that loop

- the AA, 55 (or similar) feed sequence is better than the 
alternative of not having one (but not by much!)

Brendan

--- In lpc2000@yahoogroups.com, Robert Adsett <subscriptions@a...> 
wrote:
>
> At 01:09 AM 12/11/05 -0500, Tom Walsh wrote:
> >I've been following this thread with interest as I expected to use 
the
> >watchdog in my application.  The old design used a MAX690 where you
> >would toggle the input to keep the watchdog happy.  This worked 
well for
> >us as the foreground software would set the pin high and the 
interrupt
> >routines would reset it low.  This ensured that both sections of 
the
> >program were operating okay.  Foreground did non-time-critical 
tasks
> >while the background serviced realtime critical tasks & 
communications
> >over RS485.
> >
> >I had expected to do something similar with the LPC2000 parts.  
Feed the
> >watchdog with 0xaa from the interrupt layer and then feed it with 
0x55
> >from the foreground.  It was expected that even if the watchdog 
received
> >something like this, it would still be fine:
> >
> >0xaa, 0xaa, 0xaa, 0x55, 0xaa, 0xaa, 0xaa, 0xaa, 0x55 ....
> >
> >
> >What value is a watchdog that requires you to carefully feed it, it
> >sounds as if the watchdog is very fragile?
> 
> 
> Actually, that is rather the point.  The idea is to prevent being 
able to 
> accidentally satisfy the watchdog with writes from multiple places 
in the 
> program.  Watchdogs are supposed to be somewhat twitchy.  Even so 
an 
> internal watchdog doesn't usually catch events like loss of 
> oscillator.  The Philips watchdog also appears to allow the trip 
time to be 
> reprogrammed during operation which is a big weakness.
> 
> BTW this is not an unusual requirement for microcontroller based 
watchdogs, 
> at least in my experience.
> 
> You may find (if you haven't read it already) Jack Ganssle's 
article on 
> watchdogs interesting.  http://www.ganssle.com/watchdogs.pdf
> 
> 
> 
> >I noticed that Philips
> >Applications people studiously stayed out of this thread about the
> >watchdog!  I suspect that the watchdog is severly broken and they 
did
> >not want to comment on it?
> 
> Actually, from these accounts the watchdog is fine.  The 
documentation 
> needs to be updated though.  The line referring the watchdog 
register space 
> probably needs to be updated to match the wording used for the 
PLLFEED 
> register which explicitly refers to back to back VPB writes being 
> needed.  I expect the two peripherals are using identical logic.
> 
> I wouldn't mind that period hole being fixed though, and maybe even 
seeing 
> a minimum time between feeds enforced.
> 
> Robert
> 
> " 'Freedom' has no meaning of itself.  There are always 
restrictions,   be 
> they legal, genetic, or physical.  If you don't believe me, try to 
chew a 
Show quoted textHide quoted text
> radio signal. "  -- Kelvin Throop, III
> http://www.aeolusdevelopment.com/
>

Re: Problem with watchdog

2005-12-12 by Ken Wada

>How I solved it:
>
>I have replaced all dog-feeds with
>
> mycpsr = disableIRQ();
> WDFEED = 0xAA; WDFEED = 0x55;
> restoreIRQ( mycpsr );
>
>where disableIRQ and restoreIRQ is from R O Software
Precisely my point. It appears as if this is an extra undocumented 
feature.

Ken Wada

--- In lpc2000@yahoogroups.com, Tom Walsh <tom@o...> wrote:
>
> Ake Hedman, eurosource wrote:
> 
> >OK Guys,
> >
> >I can confirm that the WD problem is solved in my case. Thanks a 
lot 
> >all!  (Description of solution below.)
> >
> >I think this definitely should be mentioned in the err data sheets 
for 
> >the affected processors (or clearly in the UM)  as the resulting 
> >symptoms are such that the problem is very hard to debug..
> >
> >Cheers
> >/Ake
> >
> >
> >How I solved it:
> >
> >I have replaced all dog-feeds with
> >
> >        mycpsr = disableIRQ();
> >        WDFEED = 0xAA; WDFEED = 0x55;
> >        restoreIRQ( mycpsr );
> >
> >where disableIRQ and restoreIRQ is from R O Software
> >
> >  
> >
> 
> I've been following this thread with interest as I expected to use 
the 
> watchdog in my application.  The old design used a MAX690 where you 
> would toggle the input to keep the watchdog happy.  This worked well 
for 
> us as the foreground software would set the pin high and the 
interrupt 
> routines would reset it low.  This ensured that both sections of the 
> program were operating okay.  Foreground did non-time-critical tasks 
> while the background serviced realtime critical tasks & 
communications 
> over RS485.
> 
> I had expected to do something similar with the LPC2000 parts.  Feed 
the 
> watchdog with 0xaa from the interrupt layer and then feed it with 
0x55 
> from the foreground.  It was expected that even if the watchdog 
received 
> something like this, it would still be fine:
> 
> 0xaa, 0xaa, 0xaa, 0x55, 0xaa, 0xaa, 0xaa, 0xaa, 0x55 ....
> 
> 
> What value is a watchdog that requires you to carefully feed it, it 
> sounds as if the watchdog is very fragile?  I noticed that Philips 
> Applications people studiously stayed out of this thread about the 
> watchdog!  I suspect that the watchdog is severly broken and they 
did 
Show quoted textHide quoted text
> not want to comment on it?
> 
> 
> Regards,
> 
> TomW
> 
> -- 
> Tom Walsh - WN3L - Embedded Systems Consultant
> http://openhardware.net, http://cyberiansoftware.com
> "Windows? No thanks, I have work to do..."
> ----------------------------------------------------
>

Re: [lpc2000] Re: Problem with watchdog

2005-12-13 by Robert Adsett

At 02:57 PM 12/12/05 +0000, brendanmurphy37 wrote:
>Jack Ganssle's paper gives one way out of this (a supervisory task
>monitoring the health of all other tasks).

I first started using that technique about 10 years ago.  My usual way is 
to have the watchdog supervisor in a periodic interrupt (sometimes the main 
clock tick) watching a number of countdown watchdog timers and flags, one 
of each for each task or process being monitored.  Each cycle of the 
supervisor decrements the countdown timers and if none of them have overrun 
feeds the watchdog.  As soon as one is no longer fed the watchdog no longer 
gets fed.

As additional protection the task countdown timers are hamming protected so 
overwrites are less likely to give valid results.  The flags usually are 
required to have some sort of sequence or specific value (ie just setting 
them to any old value is not sufficient).  As well the task timers are not 
regarded as active until they have first been fed but they cannot be turned 
off.

They can be made fancier from there but that is sufficient to put watchdogs 
in as many periodic tasks and interrupts as you can afford the overhead 
for.  In my systems that usually only amounts to a small handful that you 
want to watch anyway.

Robert

" 'Freedom' has no meaning of itself.  There are always restrictions,   be 
they legal, genetic, or physical.  If you don't believe me, try to chew a 
radio signal. "  -- Kelvin Throop, III
http://www.aeolusdevelopment.com/

Re: Problem with watchdog

2005-12-13 by brendanmurphy37

Robert,

What you suggest sounds like a good approach: the key thing that it 
achieves is to get as much coverage as possible and minimise the risk 
of false feeds to the watchdog. The challenge, as always, is to 
balance this against complexity and time to implement.

A couple of other key ideas I'd add to the mix:

- Design the system as if there's no watchdog: if you don't do this, 
you can get into the (lazy) mode of always saying "oh, the watchdog 
will sort that out.....". This is one reason I tend to encourage 
implementing the watchdog as the last feature, and not one that the 
system depends on to do its basic function. That is, get your system 
fully functional and reliable, and then add in a watchdog (after 
fully testing it of course).

- I'd strongly agree with Jack Ganssle's paper that to be really 
effective, a watchdog must reset the processor and all its 
peripherals. I haven't come up against it on the LPC2000 series, but 
other MCUs can get some of their peripherals into various locked 
states that can only be removed by an external MCU reset (i.e. the 
CPU can't clear it by resetting the device control registers). In 
other words, a simple "jump to zero", and re-initialise peripherals 
isn't guaranteed to work. It's this kind of stuff you really only 
learn from experience (and forums like this): they don't tend to 
mention it in device data sheets for some reason.

Brendan

--- In lpc2000@yahoogroups.com, Robert Adsett <subscriptions@a...> 
wrote:
>
> At 02:57 PM 12/12/05 +0000, brendanmurphy37 wrote:
> >Jack Ganssle's paper gives one way out of this (a supervisory task
> >monitoring the health of all other tasks).
> 
> I first started using that technique about 10 years ago.  My usual 
way is 
> to have the watchdog supervisor in a periodic interrupt (sometimes 
the main 
> clock tick) watching a number of countdown watchdog timers and 
flags, one 
> of each for each task or process being monitored.  Each cycle of 
the 
> supervisor decrements the countdown timers and if none of them have 
overrun 
> feeds the watchdog.  As soon as one is no longer fed the watchdog 
no longer 
> gets fed.
> 
> As additional protection the task countdown timers are hamming 
protected so 
> overwrites are less likely to give valid results.  The flags 
usually are 
> required to have some sort of sequence or specific value (ie just 
setting 
> them to any old value is not sufficient).  As well the task timers 
are not 
> regarded as active until they have first been fed but they cannot 
be turned 
> off.
> 
> They can be made fancier from there but that is sufficient to put 
watchdogs 
> in as many periodic tasks and interrupts as you can afford the 
overhead 
> for.  In my systems that usually only amounts to a small handful 
that you 
> want to watch anyway.
> 
> Robert
> 
> " 'Freedom' has no meaning of itself.  There are always 
restrictions,   be 
> they legal, genetic, or physical.  If you don't believe me, try to 
chew a 
Show quoted textHide quoted text
> radio signal. "  -- Kelvin Throop, III
> http://www.aeolusdevelopment.com/
>

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