Lpc2000

At 01:09 AM 12/11/05 -0500, Tom Walsh wrote:
>I've been following this thread with interest as I expected to use the
>watchdog in my application.  The old design used a MAX690 where you
>would toggle the input to keep the watchdog happy.  This worked well for
>us as the foreground software would set the pin high and the interrupt
>routines would reset it low.  This ensured that both sections of the
>program were operating okay.  Foreground did non-time-critical tasks
>while the background serviced realtime critical tasks & communications
>over RS485.
>
>I had expected to do something similar with the LPC2000 parts.  Feed the
>watchdog with 0xaa from the interrupt layer and then feed it with 0x55
>from the foreground.  It was expected that even if the watchdog received
>something like this, it would still be fine:
>
>0xaa, 0xaa, 0xaa, 0x55, 0xaa, 0xaa, 0xaa, 0xaa, 0x55 ....
>
>
>What value is a watchdog that requires you to carefully feed it, it
>sounds as if the watchdog is very fragile?


Actually, that is rather the point.  The idea is to prevent being able to 
accidentally satisfy the watchdog with writes from multiple places in the 
program.  Watchdogs are supposed to be somewhat twitchy.  Even so an 
internal watchdog doesn't usually catch events like loss of 
oscillator.  The Philips watchdog also appears to allow the trip time to be 
reprogrammed during operation which is a big weakness.

BTW this is not an unusual requirement for microcontroller based watchdogs, 
at least in my experience.

You may find (if you haven't read it already) Jack Ganssle's article on 
watchdogs interesting.  http://www.ganssle.com/watchdogs.pdf



>I noticed that Philips
>Applications people studiously stayed out of this thread about the
>watchdog!  I suspect that the watchdog is severly broken and they did
>not want to comment on it?

Actually, from these accounts the watchdog is fine.  The documentation 
needs to be updated though.  The line referring the watchdog register space 
probably needs to be updated to match the wording used for the PLLFEED 
register which explicitly refers to back to back VPB writes being 
needed.  I expect the two peripherals are using identical logic.

I wouldn't mind that period hole being fixed though, and maybe even seeing 
a minimum time between feeds enforced.

Robert

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