Lpc2000

On Sun, 22 Feb 2004 11:18:03 -0500, J.C. Wren wrote:

Bill Knight wrote:

> Kris
>   Thanks for spotting this.  It's the old spurious interrupt problem.
> The fix is to disable global interrupts around the first read-modify-write
> instruction.  Doing the direct write (U0IER = xxx) can still allow the 
> problem
> to happen.  What happens is the interrupt occurs and is recognized while
> the masking instruction is executing but before it has completed.  Then
> when the instruction does complete, the interrupt can't find the vector
> so uses the default.  So to fix:

[snip]

    Why should the direct write cause this problem?  The issue with 
read-modify-write makes perfect sense, but the write should be an atomic 
operation.  How would you get an interrupt between <nothing> and the write?

    --jc

==========================================================================
This problem shows up on the Coldfire list every so often.  It MAY not be
a problem on the ARM.  The idea is that the interrupt is recognized by the
hardware and scheduled to execute at the end of the instruction that is
modifying the register.  When the instruction has completed, the interrupt
is no longer there.  As I write this I relize it is less likey a problem
considering the mask being changed is in the UART while the vector being
processed is in the VIC (in hardware, after the signal coming from the
UART). The problem on the ColdFire was the mask bit was effectively in
its "VIC".  So I'm guessing that simply writing the register would also
fix the problem.

-Bill